This fixes https://github.com/enjoy-digital/litedram/issues/130 and has been tested
at 48/64/96MHz on MT41K64M16 and MT41K512M16 variants.

Also remove un-needed cd_sys2x_eb.

eth-ip will also be used to configure Ethernet IP addresss.

colorlight: Add option for etherbone ip address and LED chaser

genesys2: LiteSDCard support

platforms/ecp5: Fix slewrate configuration

The SoC reset added recently creates a path between sys_clk and pll.clkin
clock domains that is reported by the tools but that can be safely ignored.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>

When building linux-on-litex-vexriscv for OrangeCrab:

    Warning: IOBUF 'spisdcard_clk' attribute 'SLEW' is not recognised (on line 207)
    Warning: IOBUF 'spisdcard_mosi' attribute 'SLEW' is not recognised (on line 210)
    Warning: IOBUF 'spisdcard_cs_n' attribute 'SLEW' is not recognised (on line 214)
    Warning: IOBUF 'spisdcard_miso' attribute 'SLEW' is not recognised (on line 218)

Platforms using litex.build.lattice.LatticePlatform seem to support only
"SLEWRATE", not "SLEW".  Fix the few offenders in the LogicBone and
OrangeCrab platform definitions.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>

orangecrab: Run reset_timer with por/48MHz clock domain (sys clock domain is now directly reseted on usr_btn press).

Allows the USB-ACM link to stay up during reset.

./arty.py --variant=a7-35 or a7-100
./arty_s7.py --variant=s7-50 or s7-25

Useful to do tests with Diamiond.

add colorlight v8.0 PCB

Build tested with /qmtech_wukong.py --with-sdcard --with-ethernet --integrated-rom-size=0x10000 --build.

nexys4ddr: add support for litexvideo VGA Terminal

This commit adds VGA support for the Nexys A7/ Nexys 4 DDR.

The VGA is however limited to RGB443 instead of the full 12bit RGB444.
This is because IO D8 which is MSB for Blue, is also used for ETH int_n.
This makes the final output have a yellow tint.

Fix FPGA reset logic for orangecrab target