This reduces FPGA bitstream load time from Flash well below
1 second.

Thanks to mithro for the pointer to the ECP5 bistream packer
options!

This frees up additional space for new peripherals in the future.

Rework peripheral address map to fit new device
Make debug pads optional

The LiteX timer peripheral wastes resources and is not required
for operation of the BIOS on POWER SoCs.

Initial refactor of kestrel code - will be used for versa adapter board changes.

See merge request !7

This also explicitly sets the CSR stride to avoid breakage
under future LiteX upstream changes.

This change does not alter the generated HDL or bitstream.

Successfully tested with all Kestrel peripherals and Ethernet enabled

arrow_sockit: get video terminal working on VGA

targets/nexys_video: Revert clk100 to avoid breaking Linux-on-LiteX-VexRiscv (we'll remove it when the switch the simple framebuffer will be done).

alveo_u280: Fix copyrights (avoid too much cascading on Platforms/Targets) and generate reset on idelay clock domain (similarly to recent change on others Ultrascale+ boards).

Alveo U280 board

crosslink_nx_vip: Remove constraints for hard MIPI pins

arty: Add an option to enable jtagbone

targets/versa_ecp5: Fix LiteEthPHYRMGII tx/rx delays (need to be updated due to a bug fix in the ECP5RGMII PHY).

Signed-off-by: gatecat <gatecat@ds0.me>

Then adds jtagbone for arty.  I have tested with the following
litex_server and it seems to work fine.

  litex_server --jtag --jtag-config openocd_xc7_ft2232.cfg

Note, the jtagbone and etherbone may be mutually exclusive, but I am not
sure how to define that in the args.

crosslink_nx_vip: Camera IO fixes

Signed-off-by: gatecat <gatecat@ds0.me>

Signed-off-by: gatecat <gatecat@ds0.me>

targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence).