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Kestrel Collaboration
Kestrel LiteX
litex-boards
Commits
fe67766f
Commit
fe67766f
authored
Jan 04, 2021
by
Florent Kermarrec
Browse files
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Plain Diff
targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).
parent
0e3c03f2
Changes
13
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13 changed files
with
13 additions
and
13 deletions
+13
-13
litex_boards/targets/c10lprefkit.py
litex_boards/targets/c10lprefkit.py
+1
-1
litex_boards/targets/colorlight_5a_75x.py
litex_boards/targets/colorlight_5a_75x.py
+1
-1
litex_boards/targets/de0nano.py
litex_boards/targets/de0nano.py
+1
-1
litex_boards/targets/de10lite.py
litex_boards/targets/de10lite.py
+1
-1
litex_boards/targets/de10nano.py
litex_boards/targets/de10nano.py
+1
-1
litex_boards/targets/de1soc.py
litex_boards/targets/de1soc.py
+1
-1
litex_boards/targets/de2_115.py
litex_boards/targets/de2_115.py
+1
-1
litex_boards/targets/hadbadge.py
litex_boards/targets/hadbadge.py
+1
-1
litex_boards/targets/linsn_rv901t.py
litex_boards/targets/linsn_rv901t.py
+1
-1
litex_boards/targets/minispartan6.py
litex_boards/targets/minispartan6.py
+1
-1
litex_boards/targets/mist.py
litex_boards/targets/mist.py
+1
-1
litex_boards/targets/qmtech_ep4ce15.py
litex_boards/targets/qmtech_ep4ce15.py
+1
-1
litex_boards/targets/ulx3s.py
litex_boards/targets/ulx3s.py
+1
-1
No files found.
litex_boards/targets/c10lprefkit.py
View file @
fe67766f
...
...
@@ -78,7 +78,7 @@ class BaseSoC(SoCCore):
# SDR SDRAM --------------------------------------------------------------------------------
if
not
self
.
integrated_main_ram_size
:
self
.
submodules
.
sdrphy
=
GENSDRPHY
(
platform
.
request
(
"sdram"
))
self
.
submodules
.
sdrphy
=
GENSDRPHY
(
platform
.
request
(
"sdram"
)
,
sys_clk_freq
)
self
.
add_sdram
(
"sdram"
,
phy
=
self
.
sdrphy
,
module
=
MT48LC16M16
(
sys_clk_freq
,
"1:1"
),
...
...
litex_boards/targets/colorlight_5a_75x.py
View file @
fe67766f
...
...
@@ -144,7 +144,7 @@ class BaseSoC(SoCCore):
# SDR SDRAM --------------------------------------------------------------------------------
if
not
self
.
integrated_main_ram_size
:
sdrphy_cls
=
HalfRateGENSDRPHY
if
sdram_rate
==
"1:2"
else
GENSDRPHY
self
.
submodules
.
sdrphy
=
sdrphy_cls
(
platform
.
request
(
"sdram"
))
self
.
submodules
.
sdrphy
=
sdrphy_cls
(
platform
.
request
(
"sdram"
)
,
sys_clk_freq
)
if
board
==
"5a-75e"
and
revision
==
"6.0"
:
sdram_cls
=
M12L64322A
sdram_size
=
0x80000000
...
...
litex_boards/targets/de0nano.py
View file @
fe67766f
...
...
@@ -75,7 +75,7 @@ class BaseSoC(SoCCore):
# SDR SDRAM --------------------------------------------------------------------------------
if
not
self
.
integrated_main_ram_size
:
sdrphy_cls
=
HalfRateGENSDRPHY
if
sdram_rate
==
"1:2"
else
GENSDRPHY
self
.
submodules
.
sdrphy
=
sdrphy_cls
(
platform
.
request
(
"sdram"
))
self
.
submodules
.
sdrphy
=
sdrphy_cls
(
platform
.
request
(
"sdram"
)
,
sys_clk_freq
)
self
.
add_sdram
(
"sdram"
,
phy
=
self
.
sdrphy
,
module
=
IS42S16160
(
sys_clk_freq
,
sdram_rate
),
...
...
litex_boards/targets/de10lite.py
View file @
fe67766f
...
...
@@ -70,7 +70,7 @@ class BaseSoC(SoCCore):
# SDR SDRAM --------------------------------------------------------------------------------
if
not
self
.
integrated_main_ram_size
:
self
.
submodules
.
sdrphy
=
GENSDRPHY
(
platform
.
request
(
"sdram"
))
self
.
submodules
.
sdrphy
=
GENSDRPHY
(
platform
.
request
(
"sdram"
)
,
sys_clk_freq
)
self
.
add_sdram
(
"sdram"
,
phy
=
self
.
sdrphy
,
module
=
IS42S16320
(
sys_clk_freq
,
"1:1"
),
...
...
litex_boards/targets/de10nano.py
View file @
fe67766f
...
...
@@ -81,7 +81,7 @@ class BaseSoC(SoCCore):
# SDR SDRAM --------------------------------------------------------------------------------
if
with_mister_sdram
and
not
self
.
integrated_main_ram_size
:
sdrphy_cls
=
HalfRateGENSDRPHY
if
sdram_rate
==
"1:2"
else
GENSDRPHY
self
.
submodules
.
sdrphy
=
sdrphy_cls
(
platform
.
request
(
"sdram"
))
self
.
submodules
.
sdrphy
=
sdrphy_cls
(
platform
.
request
(
"sdram"
)
,
sys_clk_freq
)
self
.
add_sdram
(
"sdram"
,
phy
=
self
.
sdrphy
,
module
=
AS4C32M16
(
sys_clk_freq
,
sdram_rate
),
...
...
litex_boards/targets/de1soc.py
View file @
fe67766f
...
...
@@ -64,7 +64,7 @@ class BaseSoC(SoCCore):
# SDR SDRAM --------------------------------------------------------------------------------
if
not
self
.
integrated_main_ram_size
:
self
.
submodules
.
sdrphy
=
GENSDRPHY
(
platform
.
request
(
"sdram"
))
self
.
submodules
.
sdrphy
=
GENSDRPHY
(
platform
.
request
(
"sdram"
)
,
sys_clk_freq
)
self
.
add_sdram
(
"sdram"
,
phy
=
self
.
sdrphy
,
module
=
IS42S16320
(
sys_clk_freq
,
"1:1"
),
...
...
litex_boards/targets/de2_115.py
View file @
fe67766f
...
...
@@ -64,7 +64,7 @@ class BaseSoC(SoCCore):
# SDR SDRAM --------------------------------------------------------------------------------
if
not
self
.
integrated_main_ram_size
:
self
.
submodules
.
sdrphy
=
GENSDRPHY
(
platform
.
request
(
"sdram"
))
self
.
submodules
.
sdrphy
=
GENSDRPHY
(
platform
.
request
(
"sdram"
)
,
sys_clk_freq
)
self
.
add_sdram
(
"sdram"
,
phy
=
self
.
sdrphy
,
module
=
IS42S16320
(
self
.
clk_freq
,
"1:1"
),
...
...
litex_boards/targets/hadbadge.py
View file @
fe67766f
...
...
@@ -71,7 +71,7 @@ class BaseSoC(SoCCore):
# SDR SDRAM --------------------------------------------------------------------------------
if
not
self
.
integrated_main_ram_size
:
self
.
submodules
.
sdrphy
=
GENSDRPHY
(
platform
.
request
(
"sdram"
),
cl
=
2
)
self
.
submodules
.
sdrphy
=
GENSDRPHY
(
platform
.
request
(
"sdram"
),
sys_clk_freq
)
self
.
add_sdram
(
"sdram"
,
phy
=
self
.
sdrphy
,
module
=
AS4C32M8
(
sys_clk_freq
,
"1:1"
),
...
...
litex_boards/targets/linsn_rv901t.py
View file @
fe67766f
...
...
@@ -65,7 +65,7 @@ class BaseSoC(SoCCore):
# SDR SDRAM --------------------------------------------------------------------------------
if
not
self
.
integrated_main_ram_size
:
self
.
submodules
.
sdrphy
=
GENSDRPHY
(
platform
.
request
(
"sdram"
))
self
.
submodules
.
sdrphy
=
GENSDRPHY
(
platform
.
request
(
"sdram"
)
,
sys_clk_freq
)
self
.
add_sdram
(
"sdram"
,
phy
=
self
.
sdrphy
,
module
=
M12L64322A
(
sys_clk_freq
,
"1:1"
),
...
...
litex_boards/targets/minispartan6.py
View file @
fe67766f
...
...
@@ -78,7 +78,7 @@ class BaseSoC(SoCCore):
# SDR SDRAM --------------------------------------------------------------------------------
if
not
self
.
integrated_main_ram_size
:
sdrphy_cls
=
HalfRateGENSDRPHY
if
sdram_rate
==
"1:2"
else
GENSDRPHY
self
.
submodules
.
sdrphy
=
sdrphy_cls
(
platform
.
request
(
"sdram"
))
self
.
submodules
.
sdrphy
=
sdrphy_cls
(
platform
.
request
(
"sdram"
)
,
sys_clk_freq
)
self
.
add_sdram
(
"sdram"
,
phy
=
self
.
sdrphy
,
module
=
AS4C16M16
(
sys_clk_freq
,
sdram_rate
),
...
...
litex_boards/targets/mist.py
View file @
fe67766f
...
...
@@ -70,7 +70,7 @@ class BaseSoC(SoCCore):
# SDR SDRAM --------------------------------------------------------------------------------
if
not
self
.
integrated_main_ram_size
:
self
.
submodules
.
sdrphy
=
GENSDRPHY
(
platform
.
request
(
"sdram"
))
self
.
submodules
.
sdrphy
=
GENSDRPHY
(
platform
.
request
(
"sdram"
)
,
sys_clk_freq
)
self
.
add_sdram
(
"sdram"
,
phy
=
self
.
sdrphy
,
module
=
MT48LC16M16
(
sys_clk_freq
,
"1:1"
),
...
...
litex_boards/targets/qmtech_ep4ce15.py
View file @
fe67766f
...
...
@@ -75,7 +75,7 @@ class BaseSoC(SoCCore):
# SDR SDRAM --------------------------------------------------------------------------------
if
not
self
.
integrated_main_ram_size
:
sdrphy_cls
=
HalfRateGENSDRPHY
if
sdram_rate
==
"1:2"
else
GENSDRPHY
self
.
submodules
.
sdrphy
=
sdrphy_cls
(
platform
.
request
(
"sdram"
))
self
.
submodules
.
sdrphy
=
sdrphy_cls
(
platform
.
request
(
"sdram"
)
,
sys_clk_freq
)
self
.
add_sdram
(
"sdram"
,
phy
=
self
.
sdrphy
,
module
=
IS42S16160
(
sys_clk_freq
,
sdram_rate
),
...
...
litex_boards/targets/ulx3s.py
View file @
fe67766f
...
...
@@ -97,7 +97,7 @@ class BaseSoC(SoCCore):
# SDR SDRAM --------------------------------------------------------------------------------
if
not
self
.
integrated_main_ram_size
:
sdrphy_cls
=
HalfRateGENSDRPHY
if
sdram_rate
==
"1:2"
else
GENSDRPHY
self
.
submodules
.
sdrphy
=
sdrphy_cls
(
platform
.
request
(
"sdram"
))
self
.
submodules
.
sdrphy
=
sdrphy_cls
(
platform
.
request
(
"sdram"
)
,
sys_clk_freq
)
self
.
add_sdram
(
"sdram"
,
phy
=
self
.
sdrphy
,
module
=
getattr
(
litedram_modules
,
sdram_module_cls
)(
sys_clk_freq
,
sdram_rate
),
...
...
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