Commit fc22e28f authored by Florent Kermarrec's avatar Florent Kermarrec

targets: replace PCIeSoC with BaseSoC.

parent d28a0c42
......@@ -68,9 +68,9 @@ class CRG(Module):
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
# PCIeSoC -----------------------------------------------------------------------------------------
# BaseSoC -----------------------------------------------------------------------------------------
class PCIeSoC(SoCCore):
class BaseSoC(SoCCore):
def __init__(self, platform, **kwargs):
sys_clk_freq = int(100e6)
......@@ -171,7 +171,7 @@ def main():
args.csr_data_width = 32
platform = acorn_cle_215.Platform()
soc = PCIeSoC(platform, **soc_sdram_argdict(args))
soc = BaseSoC(platform, **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
......
......@@ -51,9 +51,9 @@ class CRG(Module):
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
# PCIeSoC -----------------------------------------------------------------------------------------
# BaseSoC -----------------------------------------------------------------------------------------
class PCIeSoC(SoCCore):
class BaseSoC(SoCCore):
def __init__(self, platform, **kwargs):
sys_clk_freq = int(100e6)
......@@ -152,7 +152,7 @@ def main():
args.csr_data_width = 32
platform = aller.Platform()
soc = PCIeSoC(platform, **soc_sdram_argdict(args))
soc = BaseSoC(platform, **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
......
......@@ -48,9 +48,9 @@ class CRG(Module):
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
# PCIeSoC -----------------------------------------------------------------------------------------
# BaseSoC -----------------------------------------------------------------------------------------
class PCIeSoC(SoCCore):
class BaseSoC(SoCCore):
def __init__(self, platform, **kwargs):
sys_clk_freq = int(100e6)
......@@ -143,7 +143,7 @@ def main():
args.csr_data_width = 32
platform = nereid.Platform()
soc = PCIeSoC(platform, **soc_sdram_argdict(args))
soc = BaseSoC(platform, **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
......
......@@ -51,9 +51,9 @@ class CRG(Module):
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
# PCIeSoC -----------------------------------------------------------------------------------------
# BaseSoC -----------------------------------------------------------------------------------------
class PCIeSoC(SoCCore):
class BaseSoC(SoCCore):
def __init__(self, platform, **kwargs):
sys_clk_freq = int(100e6)
......@@ -152,7 +152,7 @@ def main():
args.csr_data_width = 32
platform = tagus.Platform()
soc = PCIeSoC(platform, **soc_sdram_argdict(args))
soc = BaseSoC(platform, **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
......
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