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Kestrel Collaboration
Kestrel LiteX
litex-boards
Commits
f9252fdd
Commit
f9252fdd
authored
Oct 29, 2020
by
Florent Kermarrec
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targets/kc705: simplify SATA using LiteX's add_sata integration method.
parent
7da8628f
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1
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litex_boards/targets/kc705.py
litex_boards/targets/kc705.py
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litex_boards/targets/kc705.py
View file @
f9252fdd
...
...
@@ -89,11 +89,7 @@ class BaseSoC(SoCCore):
# SATA (Experimental) ----------------------------------------------------------------------
if
with_sata
:
from
litex.build.generic_platform
import
Subsignal
,
Pins
from
litex.soc.interconnect
import
wishbone
from
litesata.phy
import
LiteSATAPHY
from
litesata.core
import
LiteSATACore
from
litesata.frontend.arbitration
import
LiteSATACrossbar
from
litesata.frontend.dma
import
LiteSATABlock2MemDMA
# IOs
_sata_io
=
[
...
...
@@ -120,29 +116,10 @@ class BaseSoC(SoCCore):
gen
=
"gen2"
,
clk_freq
=
sys_clk_freq
,
data_width
=
16
)
self
.
add_csr
(
"sata_phy"
)
# Core
self
.
submodules
.
sata_core
=
LiteSATACore
(
self
.
sata_phy
)
# Crossbar
self
.
submodules
.
sata_crossbar
=
LiteSATACrossbar
(
self
.
sata_core
)
# Block2Mem DMA
bus
=
wishbone
.
Interface
(
data_width
=
32
,
adr_width
=
32
)
self
.
submodules
.
sata_block2mem
=
LiteSATABlock2MemDMA
(
user_port
=
self
.
sata_crossbar
.
get_port
(),
bus
=
bus
,
endianness
=
self
.
cpu
.
endianness
)
self
.
bus
.
add_master
(
"sata_block2mem"
,
master
=
bus
)
self
.
add_csr
(
"sata_block2mem"
)
# Timing constraints
platform
.
add_period_constraint
(
self
.
sata_phy
.
crg
.
cd_sata_tx
.
clk
,
1e9
/
150e6
)
platform
.
add_period_constraint
(
self
.
sata_phy
.
crg
.
cd_sata_tx
.
clk
,
1e9
/
150e6
)
self
.
platform
.
add_false_path_constraints
(
self
.
crg
.
cd_sys
.
clk
,
self
.
sata_phy
.
crg
.
cd_sata_tx
.
clk
,
self
.
sata_phy
.
crg
.
cd_sata_tx
.
clk
)
self
.
add_sata
(
phy
=
self
.
sata_phy
,
mode
=
"read"
)
# Leds -------------------------------------------------------------------------------------
self
.
submodules
.
leds
=
LedChaser
(
...
...
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