diff --git a/litex_boards/platforms/versa_ecp5.py b/litex_boards/platforms/versa_ecp5.py
index 67d389d0e07c2689986106bbce0961294e55b925..308b781f374738f7392a36455ccce5880d0493ac 100644
--- a/litex_boards/platforms/versa_ecp5.py
+++ b/litex_boards/platforms/versa_ecp5.py
@@ -240,18 +240,29 @@ _io = [
         Misc("DRIVE=16"),
     ),
 
-    ("debug_port_2", 0,
-        Subsignal("led_15", Pins("B19"), IOStandard("LVCMOS33")),
-        Subsignal("led_14", Pins("B9"), IOStandard("LVCMOS33")),
-        Subsignal("led_13", Pins("D6"), IOStandard("LVCMOS33")),
-        Subsignal("led_12", Pins("D7"), IOStandard("LVCMOS33")),
-        Subsignal("led_11", Pins("B6"), IOStandard("LVCMOS33")),
-        Subsignal("led_10", Pins("D9"), IOStandard("LVCMOS33")),
-        Subsignal("led_9", Pins("C8"), IOStandard("LVCMOS33")),
-        Subsignal("led_8", Pins("E8"), IOStandard("LVCMOS33")),
+    ("pwm_tach_pads", 0,
+        Subsignal("pwm1", Pins("B19"), IOStandard("LVCMOS33")),
+        Subsignal("pwm2", Pins("B9"), IOStandard("LVCMOS33")),
+        Subsignal("pwm3", Pins("D6"), IOStandard("LVCMOS33")),
+        Subsignal("pwm4", Pins("D7"), IOStandard("LVCMOS33")),
+        Subsignal("tach1", Pins("B6"), IOStandard("LVCMOS33")),
+        Subsignal("tach2", Pins("D9"), IOStandard("LVCMOS33")),
+        Subsignal("tach3", Pins("C8"), IOStandard("LVCMOS33")),
+        Subsignal("tach4", Pins("E8"), IOStandard("LVCMOS33")),
     ),
 
-    ("lpc_debug_mirror_clock", 0, Pins("E12"), IOStandard("LVCMOS33"))
+    #("debug_port_2", 0,
+        #Subsignal("led_15", Pins("B19"), IOStandard("LVCMOS33")),
+        #Subsignal("led_14", Pins("B9"), IOStandard("LVCMOS33")),
+        #Subsignal("led_13", Pins("D6"), IOStandard("LVCMOS33")),
+        #Subsignal("led_12", Pins("D7"), IOStandard("LVCMOS33")),
+        #Subsignal("led_11", Pins("B6"), IOStandard("LVCMOS33")),
+        #Subsignal("led_10", Pins("D9"), IOStandard("LVCMOS33")),
+        #Subsignal("led_9", Pins("C8"), IOStandard("LVCMOS33")),
+        #Subsignal("led_8", Pins("E8"), IOStandard("LVCMOS33")),
+    #),
+
+    #("lpc_debug_mirror_clock", 0, Pins("E12"), IOStandard("LVCMOS33"))
 ]
 
 # ECP5-hat extension (https://github.com/daveshah1/ecp5-hat) ---------------------------------------
diff --git a/litex_boards/targets/versa_ecp5.py b/litex_boards/targets/versa_ecp5.py
index 3164ad15f0d2ab0066e9b630f348ead2f5749231..a4ab405390801d01c1a1e4e23f2d6212251fb5ea 100755
--- a/litex_boards/targets/versa_ecp5.py
+++ b/litex_boards/targets/versa_ecp5.py
@@ -37,6 +37,7 @@ from tercelspi.tercelspi import TercelSPI
 from aquilalpc.aquilalpc import AquilaLPCSlave
 from swiftfsi.swiftfsi import OpenFSIMaster
 from simplertc.simplertc import SimpleRTCSlave
+from simplepwm.simplepwm import SimplePWMSlave
 from opencoresi2c.opencoresi2c import OpenCoresI2CMaster
 
 # Useful constants
@@ -101,6 +102,7 @@ class BaseSoC(SoCCore):
         "bmcspiflashcfg"  : 0xc3004000,
         "hostspiflashcfg" : 0xc3005000,
         "simplertc"       : 0xc3006000,
+        "simplepwm"       : 0xc3006800,
         "openfsimaster"   : 0xc3007000,
         "i2cmaster1"      : 0xc3008000,
         "i2cmaster2"      : 0xc3008020,
@@ -124,7 +126,7 @@ class BaseSoC(SoCCore):
     }
     interrupt_map.update(SoCCore.interrupt_map)
 
-    def __init__(self, sys_clk_freq=int(50e6), device="LFE5UM5G", with_ethernet=False, with_etherbone=False, with_openfsi_master=True, with_bmcspiflash=True, with_hostspiflash=True, with_hostlpcslave=True, with_i2c_masters=True, with_simple_rtc=True, eth_ip="192.168.1.50", eth_phy=0, toolchain="trellis", **kwargs):
+    def __init__(self, sys_clk_freq=int(50e6), device="LFE5UM5G", with_ethernet=False, with_etherbone=False, with_openfsi_master=True, with_bmcspiflash=True, with_hostspiflash=True, with_hostlpcslave=True, with_i2c_masters=True, with_simple_pwm=True, with_simple_rtc=True, eth_ip="192.168.1.50", eth_phy=0, toolchain="trellis", **kwargs):
         platform = versa_ecp5.Platform(toolchain=toolchain, device=device)
 
         # Reduce resource wastage on ECP5
@@ -317,6 +319,20 @@ class BaseSoC(SoCCore):
             if platform.request("i2c_master", None, True):
                 raise ValueError("Unhandled i2c_master found")
 
+        # SimplePWM --------------------------------------------------------------------------------
+        if with_simple_pwm:
+            pwm_tach_pads = platform.request("pwm_tach_pads")
+            self.submodules.simple_pwm = SimplePWMSlave(
+                platform        = platform,
+                pads            = pwm_tach_pads,
+                endianness      = self.cpu.endianness,
+                pwm_clk_src     = 'sys',
+                pwm_clk_freq    = sys_clk_freq)
+            self.add_csr("simplepwm")
+            simple_pwm_size = 128
+            simple_pwm_region = SoCRegion(origin=self.mem_map.get("simplepwm", None), size=simple_pwm_size, cached=False)
+            self.bus.add_slave(name="simplepwm", slave=self.simple_pwm.slave_bus, region=simple_pwm_region)
+
         # SimpleRTC --------------------------------------------------------------------------------
         if with_simple_rtc:
             self.submodules.simple_rtc = SimpleRTCSlave(
@@ -409,6 +425,7 @@ def main():
         with_hostlpcslave = True,
         with_openfsi_master = True,
         with_i2c_masters = True,
+        with_simple_pwm = True,
         with_simple_rtc = True,
         eth_ip         = args.eth_ip,
         eth_phy        = args.eth_phy,
@@ -417,12 +434,10 @@ def main():
     )
     builder = Builder(soc, **builder_argdict(args))
 
-
     # Flash boot setup
     flash_boot_adr = soc.mem_map["bmcspiflash"] + 0x800000
     soc.add_constant("FLASH_BOOT_ADDRESS", flash_boot_adr)
 
-
     soc.set_gateware_dir(builder.gateware_dir)
 
     builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}