Commit f66860c2 authored by Alessandro Comodi's avatar Alessandro Comodi

zybo_z7: fix clock pin constraint

Signed-off-by: default avatarAlessandro Comodi <acomodi@antmicro.com>
parent 26d3b572
......@@ -11,7 +11,7 @@ from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
_io = [
# Clk / Rst
("clk125", 0, Pins("L16"), IOStandard("LVCMOS33")),
("clk125", 0, Pins("K17"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("M14"), IOStandard("LVCMOS33")),
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment