Commit e91a5d6b authored by Florent Kermarrec's avatar Florent Kermarrec

targets/pcie: remove soft reset.

parent 1356ebb4
......@@ -26,7 +26,6 @@ import argparse
import sys
from migen import *
from migen.genlib.misc import WaitTimer
from litex_boards.platforms import acorn_cle_215
......@@ -52,10 +51,8 @@ from litepcie.software import generate_litepcie_software
# CRG ----------------------------------------------------------------------------------------------
class CRG(Module, AutoCSR):
class CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.rst = CSR()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
......@@ -64,14 +61,8 @@ class CRG(Module, AutoCSR):
# Clk/Rst
clk200 = platform.request("clk200")
# Delay software reset by 10us to ensure write has been acked on PCIe.
rst_delay = WaitTimer(int(10e-6*sys_clk_freq))
self.submodules += rst_delay
self.sync += If(self.rst.re, rst_delay.wait.eq(1))
# PLL
self.submodules.pll = pll = S7PLL()
self.comb += pll.reset.eq(rst_delay.done)
pll.register_clkin(clk200, 200e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
......
......@@ -9,7 +9,6 @@ import argparse
import sys
from migen import *
from migen.genlib.misc import WaitTimer
from litex_boards.platforms import aller
......@@ -35,10 +34,8 @@ from litepcie.software import generate_litepcie_software
# CRG ----------------------------------------------------------------------------------------------
class CRG(Module, AutoCSR):
class CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.rst = CSR()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
......@@ -47,14 +44,8 @@ class CRG(Module, AutoCSR):
# Clk/Rst
clk100 = platform.request("clk100")
# Delay software reset by 10us to ensure write has been acked on PCIe.
rst_delay = WaitTimer(int(10e-6*sys_clk_freq))
self.submodules += rst_delay
self.sync += If(self.rst.re, rst_delay.wait.eq(1))
# PLL
self.submodules.pll = pll = S7PLL()
self.comb += pll.reset.eq(rst_delay.done)
pll.register_clkin(clk100, 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
......
......@@ -9,7 +9,6 @@ import argparse
import sys
from migen import *
from migen.genlib.misc import WaitTimer
from litex_boards.platforms import nereid
......@@ -34,10 +33,8 @@ from litepcie.software import generate_litepcie_software
# CRG ----------------------------------------------------------------------------------------------
class CRG(Module, AutoCSR):
class CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.rst = CSR()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain()
......@@ -45,14 +42,8 @@ class CRG(Module, AutoCSR):
# Clk/Rst
clk100 = platform.request("clk100")
# Delay software reset by 10us to ensure write has been acked on PCIe.
rst_delay = WaitTimer(int(10e-6*sys_clk_freq))
self.submodules += rst_delay
self.sync += If(self.rst.re, rst_delay.wait.eq(1))
# PLL
self.submodules.pll = pll = S7PLL()
self.comb += pll.reset.eq(rst_delay.done)
pll.register_clkin(clk100, 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
......
......@@ -9,7 +9,6 @@ import argparse
import sys
from migen import *
from migen.genlib.misc import WaitTimer
from litex_boards.platforms import tagus
......@@ -35,10 +34,8 @@ from litepcie.software import generate_litepcie_software
# CRG ----------------------------------------------------------------------------------------------
class CRG(Module, AutoCSR):
class CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.rst = CSR()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
......@@ -47,14 +44,8 @@ class CRG(Module, AutoCSR):
# Clk/Rst
clk100 = platform.request("clk100")
# Delay software reset by 10us to ensure write has been acked on PCIe.
rst_delay = WaitTimer(int(10e-6*sys_clk_freq))
self.submodules += rst_delay
self.sync += If(self.rst.re, rst_delay.wait.eq(1))
# PLL
self.submodules.pll = pll = S7PLL()
self.comb += pll.reset.eq(rst_delay.done)
pll.register_clkin(clk100, 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
......
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