Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Support
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in / Register
Toggle navigation
L
litex-boards
Project overview
Project overview
Details
Activity
Releases
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Issues
0
Issues
0
List
Boards
Labels
Milestones
Merge Requests
1
Merge Requests
1
Analytics
Analytics
Repository
Value Stream
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Create a new issue
Commits
Issue Boards
Open sidebar
Kestrel Collaboration
Kestrel LiteX
litex-boards
Commits
d73bd2f7
Commit
d73bd2f7
authored
Jan 07, 2021
by
Florent Kermarrec
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
targets/xilinx: add comment on sys_clk to pll.clkin false path.
parent
1ac1c685
Changes
28
Hide whitespace changes
Inline
Side-by-side
Showing
28 changed files
with
28 additions
and
28 deletions
+28
-28
litex_boards/targets/ac701.py
litex_boards/targets/ac701.py
+1
-1
litex_boards/targets/acorn_cle_215.py
litex_boards/targets/acorn_cle_215.py
+1
-1
litex_boards/targets/aller.py
litex_boards/targets/aller.py
+1
-1
litex_boards/targets/alveo_u250.py
litex_boards/targets/alveo_u250.py
+1
-1
litex_boards/targets/arty.py
litex_boards/targets/arty.py
+1
-1
litex_boards/targets/arty_s7.py
litex_boards/targets/arty_s7.py
+1
-1
litex_boards/targets/fk33.py
litex_boards/targets/fk33.py
+1
-1
litex_boards/targets/genesys2.py
litex_boards/targets/genesys2.py
+1
-1
litex_boards/targets/kc705.py
litex_boards/targets/kc705.py
+1
-1
litex_boards/targets/kcu105.py
litex_boards/targets/kcu105.py
+1
-1
litex_boards/targets/kx2.py
litex_boards/targets/kx2.py
+1
-1
litex_boards/targets/litefury.py
litex_boards/targets/litefury.py
+1
-1
litex_boards/targets/mercury_xu5.py
litex_boards/targets/mercury_xu5.py
+1
-1
litex_boards/targets/mimas_a7.py
litex_boards/targets/mimas_a7.py
+1
-1
litex_boards/targets/minispartan6.py
litex_boards/targets/minispartan6.py
+1
-1
litex_boards/targets/nereid.py
litex_boards/targets/nereid.py
+1
-1
litex_boards/targets/netv2.py
litex_boards/targets/netv2.py
+1
-1
litex_boards/targets/nexys4ddr.py
litex_boards/targets/nexys4ddr.py
+1
-1
litex_boards/targets/nexys_video.py
litex_boards/targets/nexys_video.py
+1
-1
litex_boards/targets/pano_logic_g2.py
litex_boards/targets/pano_logic_g2.py
+1
-1
litex_boards/targets/redpitaya.py
litex_boards/targets/redpitaya.py
+1
-1
litex_boards/targets/sds1104xe.py
litex_boards/targets/sds1104xe.py
+1
-1
litex_boards/targets/tagus.py
litex_boards/targets/tagus.py
+1
-1
litex_boards/targets/vc707.py
litex_boards/targets/vc707.py
+1
-1
litex_boards/targets/vcu118.py
litex_boards/targets/vcu118.py
+1
-1
litex_boards/targets/xcu1525.py
litex_boards/targets/xcu1525.py
+1
-1
litex_boards/targets/zcu104.py
litex_boards/targets/zcu104.py
+1
-1
litex_boards/targets/zybo_z7.py
litex_boards/targets/zybo_z7.py
+1
-1
No files found.
litex_boards/targets/ac701.py
View file @
d73bd2f7
...
...
@@ -50,7 +50,7 @@ class _CRG(Module):
pll
.
create_clkout
(
self
.
cd_sys4x
,
4
*
sys_clk_freq
)
pll
.
create_clkout
(
self
.
cd_sys4x_dqs
,
4
*
sys_clk_freq
,
phase
=
90
)
pll
.
create_clkout
(
self
.
cd_idelay
,
200e6
)
platform
.
add_false_path_constraints
(
pll
.
clkin
,
self
.
cd_sys
.
clk
)
platform
.
add_false_path_constraints
(
self
.
cd_sys
.
clk
,
pll
.
clkin
)
# Ignore sys_clk to pll.clkin path created by SoC's rst.
self
.
submodules
.
idelayctrl
=
S7IDELAYCTRL
(
self
.
cd_idelay
)
...
...
litex_boards/targets/acorn_cle_215.py
View file @
d73bd2f7
...
...
@@ -66,7 +66,7 @@ class CRG(Module):
pll
.
create_clkout
(
self
.
cd_sys4x
,
4
*
sys_clk_freq
)
pll
.
create_clkout
(
self
.
cd_sys4x_dqs
,
4
*
sys_clk_freq
,
phase
=
90
)
pll
.
create_clkout
(
self
.
cd_idelay
,
200e6
)
platform
.
add_false_path_constraints
(
pll
.
clkin
,
self
.
cd_sys
.
clk
)
platform
.
add_false_path_constraints
(
self
.
cd_sys
.
clk
,
pll
.
clkin
)
# Ignore sys_clk to pll.clkin path created by SoC's rst.
self
.
submodules
.
idelayctrl
=
S7IDELAYCTRL
(
self
.
cd_idelay
)
...
...
litex_boards/targets/aller.py
View file @
d73bd2f7
...
...
@@ -50,7 +50,7 @@ class CRG(Module):
pll
.
create_clkout
(
self
.
cd_sys4x
,
4
*
sys_clk_freq
)
pll
.
create_clkout
(
self
.
cd_sys4x_dqs
,
4
*
sys_clk_freq
,
phase
=
90
)
pll
.
create_clkout
(
self
.
cd_idelay
,
200e6
)
platform
.
add_false_path_constraints
(
pll
.
clkin
,
self
.
cd_sys
.
clk
)
platform
.
add_false_path_constraints
(
self
.
cd_sys
.
clk
,
pll
.
clkin
)
# Ignore sys_clk to pll.clkin path created by SoC's rst.
self
.
submodules
.
idelayctrl
=
S7IDELAYCTRL
(
self
.
cd_idelay
)
...
...
litex_boards/targets/alveo_u250.py
View file @
d73bd2f7
...
...
@@ -44,7 +44,7 @@ class _CRG(Module):
pll
.
register_clkin
(
platform
.
request
(
"clk300"
,
0
),
300e6
)
pll
.
create_clkout
(
self
.
cd_pll4x
,
sys_clk_freq
*
4
,
buf
=
None
,
with_reset
=
False
)
pll
.
create_clkout
(
self
.
cd_idelay
,
500e6
,
with_reset
=
False
)
platform
.
add_false_path_constraints
(
pll
.
clkin
,
self
.
cd_sys
.
clk
)
platform
.
add_false_path_constraints
(
self
.
cd_sys
.
clk
,
pll
.
clkin
)
# Ignore sys_clk to pll.clkin path created by SoC's rst.
self
.
specials
+=
[
Instance
(
"BUFGCE_DIV"
,
name
=
"main_bufgce_div"
,
...
...
litex_boards/targets/arty.py
View file @
d73bd2f7
...
...
@@ -47,7 +47,7 @@ class _CRG(Module):
pll
.
create_clkout
(
self
.
cd_sys4x_dqs
,
4
*
sys_clk_freq
,
phase
=
90
)
pll
.
create_clkout
(
self
.
cd_idelay
,
200e6
)
pll
.
create_clkout
(
self
.
cd_eth
,
25e6
)
platform
.
add_false_path_constraints
(
pll
.
clkin
,
self
.
cd_sys
.
clk
)
platform
.
add_false_path_constraints
(
self
.
cd_sys
.
clk
,
pll
.
clkin
)
# Ignore sys_clk to pll.clkin path created by SoC's rst.
self
.
submodules
.
idelayctrl
=
S7IDELAYCTRL
(
self
.
cd_idelay
)
...
...
litex_boards/targets/arty_s7.py
View file @
d73bd2f7
...
...
@@ -45,7 +45,7 @@ class _CRG(Module):
pll
.
create_clkout
(
self
.
cd_sys4x
,
4
*
sys_clk_freq
)
pll
.
create_clkout
(
self
.
cd_sys4x_dqs
,
4
*
sys_clk_freq
,
phase
=
90
)
pll
.
create_clkout
(
self
.
cd_idelay
,
200e6
)
platform
.
add_false_path_constraints
(
pll
.
clkin
,
self
.
cd_sys
.
clk
)
platform
.
add_false_path_constraints
(
self
.
cd_sys
.
clk
,
pll
.
clkin
)
# Ignore sys_clk to pll.clkin path created by SoC's rst.
self
.
submodules
.
idelayctrl
=
S7IDELAYCTRL
(
self
.
cd_idelay
)
...
...
litex_boards/targets/fk33.py
View file @
d73bd2f7
...
...
@@ -38,7 +38,7 @@ class _CRG(Module):
self
.
comb
+=
pll
.
reset
.
eq
(
self
.
rst
)
pll
.
register_clkin
(
platform
.
request
(
"clk200"
),
200e6
)
pll
.
create_clkout
(
self
.
cd_sys
,
sys_clk_freq
)
platform
.
add_false_path_constraints
(
pll
.
clkin
,
self
.
cd_sys
.
clk
)
platform
.
add_false_path_constraints
(
self
.
cd_sys
.
clk
,
pll
.
clkin
)
# Ignore sys_clk to pll.clkin path created by SoC's rst.
# BaseSoC ------------------------------------------------------------------------------------------
...
...
litex_boards/targets/genesys2.py
View file @
d73bd2f7
...
...
@@ -41,7 +41,7 @@ class _CRG(Module):
pll
.
create_clkout
(
self
.
cd_sys
,
sys_clk_freq
)
pll
.
create_clkout
(
self
.
cd_sys4x
,
4
*
sys_clk_freq
)
pll
.
create_clkout
(
self
.
cd_idelay
,
200e6
)
platform
.
add_false_path_constraints
(
pll
.
clkin
,
self
.
cd_sys
.
clk
)
platform
.
add_false_path_constraints
(
self
.
cd_sys
.
clk
,
pll
.
clkin
)
# Ignore sys_clk to pll.clkin path created by SoC's rst.
self
.
submodules
.
idelayctrl
=
S7IDELAYCTRL
(
self
.
cd_idelay
)
...
...
litex_boards/targets/kc705.py
View file @
d73bd2f7
...
...
@@ -46,7 +46,7 @@ class _CRG(Module):
pll
.
create_clkout
(
self
.
cd_sys
,
sys_clk_freq
)
pll
.
create_clkout
(
self
.
cd_sys4x
,
4
*
sys_clk_freq
)
pll
.
create_clkout
(
self
.
cd_idelay
,
200e6
)
platform
.
add_false_path_constraints
(
pll
.
clkin
,
self
.
cd_sys
.
clk
)
platform
.
add_false_path_constraints
(
self
.
cd_sys
.
clk
,
pll
.
clkin
)
# Ignore sys_clk to pll.clkin path created by SoC's rst.
self
.
submodules
.
idelayctrl
=
S7IDELAYCTRL
(
self
.
cd_idelay
)
...
...
litex_boards/targets/kcu105.py
View file @
d73bd2f7
...
...
@@ -47,7 +47,7 @@ class _CRG(Module):
pll
.
create_clkout
(
self
.
cd_pll4x
,
sys_clk_freq
*
4
,
buf
=
None
,
with_reset
=
False
)
pll
.
create_clkout
(
self
.
cd_idelay
,
200e6
,
with_reset
=
False
)
pll
.
create_clkout
(
self
.
cd_eth
,
200e6
)
platform
.
add_false_path_constraints
(
pll
.
clkin
,
self
.
cd_sys
.
clk
)
platform
.
add_false_path_constraints
(
self
.
cd_sys
.
clk
,
pll
.
clkin
)
# Ignore sys_clk to pll.clkin path created by SoC's rst.
self
.
specials
+=
[
Instance
(
"BUFGCE_DIV"
,
name
=
"main_bufgce_div"
,
...
...
litex_boards/targets/kx2.py
View file @
d73bd2f7
...
...
@@ -39,7 +39,7 @@ class _CRG(Module):
pll
.
create_clkout
(
self
.
cd_sys
,
sys_clk_freq
)
pll
.
create_clkout
(
self
.
cd_sys4x
,
4
*
sys_clk_freq
)
pll
.
create_clkout
(
self
.
cd_idelay
,
200e6
)
platform
.
add_false_path_constraints
(
pll
.
clkin
,
self
.
cd_sys
.
clk
)
platform
.
add_false_path_constraints
(
self
.
cd_sys
.
clk
,
pll
.
clkin
)
# Ignore sys_clk to pll.clkin path created by SoC's rst.
self
.
submodules
.
idelayctrl
=
S7IDELAYCTRL
(
self
.
cd_idelay
)
...
...
litex_boards/targets/litefury.py
View file @
d73bd2f7
...
...
@@ -50,7 +50,7 @@ class CRG(Module):
pll
.
create_clkout
(
self
.
cd_sys4x
,
4
*
sys_clk_freq
)
pll
.
create_clkout
(
self
.
cd_sys4x_dqs
,
4
*
sys_clk_freq
,
phase
=
90
)
pll
.
create_clkout
(
self
.
cd_idelay
,
200e6
)
platform
.
add_false_path_constraints
(
pll
.
clkin
,
self
.
cd_sys
.
clk
)
platform
.
add_false_path_constraints
(
self
.
cd_sys
.
clk
,
pll
.
clkin
)
# Ignore sys_clk to pll.clkin path created by SoC's rst.
self
.
submodules
.
idelayctrl
=
S7IDELAYCTRL
(
self
.
cd_idelay
)
...
...
litex_boards/targets/mercury_xu5.py
View file @
d73bd2f7
...
...
@@ -40,7 +40,7 @@ class _CRG(Module):
pll
.
register_clkin
(
platform
.
request
(
"clk100"
),
100e6
)
pll
.
create_clkout
(
self
.
cd_pll4x
,
sys_clk_freq
*
4
,
buf
=
None
,
with_reset
=
False
)
pll
.
create_clkout
(
self
.
cd_idelay
,
500e6
,
with_reset
=
False
)
platform
.
add_false_path_constraints
(
pll
.
clkin
,
self
.
cd_sys
.
clk
)
platform
.
add_false_path_constraints
(
self
.
cd_sys
.
clk
,
pll
.
clkin
)
# Ignore sys_clk to pll.clkin path created by SoC's rst.
self
.
specials
+=
[
Instance
(
"BUFGCE_DIV"
,
name
=
"main_bufgce_div"
,
...
...
litex_boards/targets/mimas_a7.py
View file @
d73bd2f7
...
...
@@ -45,7 +45,7 @@ class _CRG(Module):
pll
.
create_clkout
(
self
.
cd_sys4x
,
4
*
sys_clk_freq
)
pll
.
create_clkout
(
self
.
cd_sys4x_dqs
,
4
*
sys_clk_freq
,
phase
=
90
)
pll
.
create_clkout
(
self
.
cd_idelay
,
200e6
)
platform
.
add_false_path_constraints
(
pll
.
clkin
,
self
.
cd_sys
.
clk
)
platform
.
add_false_path_constraints
(
self
.
cd_sys
.
clk
,
pll
.
clkin
)
# Ignore sys_clk to pll.clkin path created by SoC's rst.
self
.
submodules
.
idelayctrl
=
S7IDELAYCTRL
(
self
.
cd_idelay
)
...
...
litex_boards/targets/minispartan6.py
View file @
d73bd2f7
...
...
@@ -55,7 +55,7 @@ class _CRG(Module):
pll
.
create_clkout
(
self
.
cd_sys2x_ps
,
2
*
sys_clk_freq
,
phase
=
90
)
else
:
pll
.
create_clkout
(
self
.
cd_sys_ps
,
sys_clk_freq
,
phase
=
90
)
platform
.
add_false_path_constraints
(
pll
.
clkin
,
self
.
cd_sys
.
clk
)
platform
.
add_false_path_constraints
(
self
.
cd_sys
.
clk
,
pll
.
clkin
)
# Ignore sys_clk to pll.clkin path created by SoC's rst.
# SDRAM clock
sdram_clk
=
ClockSignal
(
"sys2x_ps"
if
sdram_rate
==
"1:2"
else
"sys_ps"
)
...
...
litex_boards/targets/nereid.py
View file @
d73bd2f7
...
...
@@ -47,7 +47,7 @@ class CRG(Module):
pll
.
create_clkout
(
self
.
cd_sys
,
sys_clk_freq
)
pll
.
create_clkout
(
self
.
cd_sys4x
,
4
*
sys_clk_freq
)
pll
.
create_clkout
(
self
.
cd_idelay
,
200e6
)
platform
.
add_false_path_constraints
(
pll
.
clkin
,
self
.
cd_sys
.
clk
)
platform
.
add_false_path_constraints
(
self
.
cd_sys
.
clk
,
pll
.
clkin
)
# Ignore sys_clk to pll.clkin path created by SoC's rst.
self
.
submodules
.
idelayctrl
=
S7IDELAYCTRL
(
self
.
cd_idelay
)
...
...
litex_boards/targets/netv2.py
View file @
d73bd2f7
...
...
@@ -55,7 +55,7 @@ class _CRG(Module):
pll
.
create_clkout
(
self
.
cd_idelay
,
200e6
)
pll
.
create_clkout
(
self
.
cd_clk100
,
100e6
)
pll
.
create_clkout
(
self
.
cd_eth
,
50e6
)
platform
.
add_false_path_constraints
(
pll
.
clkin
,
self
.
cd_sys
.
clk
)
platform
.
add_false_path_constraints
(
self
.
cd_sys
.
clk
,
pll
.
clkin
)
# Ignore sys_clk to pll.clkin path created by SoC's rst.
self
.
submodules
.
idelayctrl
=
S7IDELAYCTRL
(
self
.
cd_idelay
)
...
...
litex_boards/targets/nexys4ddr.py
View file @
d73bd2f7
...
...
@@ -49,7 +49,7 @@ class _CRG(Module):
pll
.
create_clkout
(
self
.
cd_idelay
,
200e6
)
pll
.
create_clkout
(
self
.
cd_eth
,
50e6
)
pll
.
create_clkout
(
self
.
cd_vga
,
25e6
)
platform
.
add_false_path_constraints
(
pll
.
clkin
,
self
.
cd_sys
.
clk
)
platform
.
add_false_path_constraints
(
self
.
cd_sys
.
clk
,
pll
.
clkin
)
# Ignore sys_clk to pll.clkin path created by SoC's rst.
self
.
submodules
.
idelayctrl
=
S7IDELAYCTRL
(
self
.
cd_idelay
)
...
...
litex_boards/targets/nexys_video.py
View file @
d73bd2f7
...
...
@@ -45,7 +45,7 @@ class _CRG(Module):
pll
.
create_clkout
(
self
.
cd_sys4x_dqs
,
4
*
sys_clk_freq
,
phase
=
90
)
pll
.
create_clkout
(
self
.
cd_idelay
,
200e6
)
pll
.
create_clkout
(
self
.
cd_clk100
,
100e6
)
platform
.
add_false_path_constraints
(
pll
.
clkin
,
self
.
cd_sys
.
clk
)
platform
.
add_false_path_constraints
(
self
.
cd_sys
.
clk
,
pll
.
clkin
)
# Ignore sys_clk to pll.clkin path created by SoC's rst.
self
.
submodules
.
idelayctrl
=
S7IDELAYCTRL
(
self
.
cd_idelay
)
...
...
litex_boards/targets/pano_logic_g2.py
View file @
d73bd2f7
...
...
@@ -39,7 +39,7 @@ class _CRG(Module):
self
.
comb
+=
pll
.
reset
.
eq
(
~
platform
.
request
(
"user_btn_n"
)
|
self
.
rst
)
pll
.
register_clkin
(
platform
.
request
(
"clk125"
),
125e6
)
pll
.
create_clkout
(
self
.
cd_sys
,
clk_freq
)
platform
.
add_false_path_constraints
(
pll
.
clkin
,
self
.
cd_sys
.
clk
)
platform
.
add_false_path_constraints
(
self
.
cd_sys
.
clk
,
pll
.
clkin
)
# Ignore sys_clk to pll.clkin path created by SoC's rst.
# BaseSoC ------------------------------------------------------------------------------------------
...
...
litex_boards/targets/redpitaya.py
View file @
d73bd2f7
...
...
@@ -41,7 +41,7 @@ class _CRG(Module):
self
.
comb
+=
pll
.
reset
.
eq
(
self
.
rst
)
pll
.
register_clkin
(
platform
.
request
(
platform
.
default_clk_name
),
platform
.
default_clk_freq
)
pll
.
create_clkout
(
self
.
cd_sys
,
sys_clk_freq
)
platform
.
add_false_path_constraints
(
pll
.
clkin
,
self
.
cd_sys
.
clk
)
platform
.
add_false_path_constraints
(
self
.
cd_sys
.
clk
,
pll
.
clkin
)
# Ignore sys_clk to pll.clkin path created by SoC's rst.
# BaseSoC ------------------------------------------------------------------------------------------
...
...
litex_boards/targets/sds1104xe.py
View file @
d73bd2f7
...
...
@@ -54,7 +54,7 @@ class _CRG(Module):
pll
.
create_clkout
(
self
.
cd_sys4x
,
4
*
sys_clk_freq
)
pll
.
create_clkout
(
self
.
cd_sys4x_dqs
,
4
*
sys_clk_freq
,
phase
=
90
)
pll
.
create_clkout
(
self
.
cd_idelay
,
200e6
)
platform
.
add_false_path_constraints
(
pll
.
clkin
,
self
.
cd_sys
.
clk
)
platform
.
add_false_path_constraints
(
self
.
cd_sys
.
clk
,
pll
.
clkin
)
# Ignore sys_clk to pll.clkin path created by SoC's rst.
self
.
submodules
.
idelayctrl
=
S7IDELAYCTRL
(
self
.
cd_idelay
)
...
...
litex_boards/targets/tagus.py
View file @
d73bd2f7
...
...
@@ -51,7 +51,7 @@ class CRG(Module):
pll
.
create_clkout
(
self
.
cd_sys4x
,
4
*
sys_clk_freq
)
pll
.
create_clkout
(
self
.
cd_sys4x_dqs
,
4
*
sys_clk_freq
,
phase
=
90
)
pll
.
create_clkout
(
self
.
cd_idelay
,
200e6
)
platform
.
add_false_path_constraints
(
pll
.
clkin
,
self
.
cd_sys
.
clk
)
platform
.
add_false_path_constraints
(
self
.
cd_sys
.
clk
,
pll
.
clkin
)
# Ignore sys_clk to pll.clkin path created by SoC's rst.
self
.
submodules
.
idelayctrl
=
S7IDELAYCTRL
(
self
.
cd_idelay
)
...
...
litex_boards/targets/vc707.py
View file @
d73bd2f7
...
...
@@ -42,7 +42,7 @@ class _CRG(Module):
pll
.
create_clkout
(
self
.
cd_sys
,
sys_clk_freq
)
pll
.
create_clkout
(
self
.
cd_sys4x
,
4
*
sys_clk_freq
)
pll
.
create_clkout
(
self
.
cd_idelay
,
200e6
)
platform
.
add_false_path_constraints
(
pll
.
clkin
,
self
.
cd_sys
.
clk
)
platform
.
add_false_path_constraints
(
self
.
cd_sys
.
clk
,
pll
.
clkin
)
# Ignore sys_clk to pll.clkin path created by SoC's rst.
self
.
submodules
.
idelayctrl
=
S7IDELAYCTRL
(
self
.
cd_idelay
)
...
...
litex_boards/targets/vcu118.py
View file @
d73bd2f7
...
...
@@ -41,7 +41,7 @@ class _CRG(Module):
pll
.
register_clkin
(
platform
.
request
(
"clk125"
),
125e6
)
pll
.
create_clkout
(
self
.
cd_pll4x
,
sys_clk_freq
*
4
,
buf
=
None
,
with_reset
=
False
)
pll
.
create_clkout
(
self
.
cd_idelay
,
500e6
,
with_reset
=
False
)
platform
.
add_false_path_constraints
(
pll
.
clkin
,
self
.
cd_sys
.
clk
)
platform
.
add_false_path_constraints
(
self
.
cd_sys
.
clk
,
pll
.
clkin
)
# Ignore sys_clk to pll.clkin path created by SoC's rst.
self
.
specials
+=
[
Instance
(
"BUFGCE_DIV"
,
name
=
"main_bufgce_div"
,
...
...
litex_boards/targets/xcu1525.py
View file @
d73bd2f7
...
...
@@ -43,7 +43,7 @@ class _CRG(Module):
pll
.
register_clkin
(
platform
.
request
(
"clk300"
,
ddram_channel
),
300e6
)
pll
.
create_clkout
(
self
.
cd_pll4x
,
sys_clk_freq
*
4
,
buf
=
None
,
with_reset
=
False
)
pll
.
create_clkout
(
self
.
cd_idelay
,
500e6
,
with_reset
=
False
)
platform
.
add_false_path_constraints
(
pll
.
clkin
,
self
.
cd_sys
.
clk
)
platform
.
add_false_path_constraints
(
self
.
cd_sys
.
clk
,
pll
.
clkin
)
# Ignore sys_clk to pll.clkin path created by SoC's rst.
self
.
specials
+=
[
Instance
(
"BUFGCE_DIV"
,
name
=
"main_bufgce_div"
,
...
...
litex_boards/targets/zcu104.py
View file @
d73bd2f7
...
...
@@ -42,7 +42,7 @@ class _CRG(Module):
pll
.
register_clkin
(
platform
.
request
(
"clk125"
),
125e6
)
pll
.
create_clkout
(
self
.
cd_pll4x
,
sys_clk_freq
*
4
,
buf
=
None
,
with_reset
=
False
)
pll
.
create_clkout
(
self
.
cd_idelay
,
500e6
,
with_reset
=
False
)
platform
.
add_false_path_constraints
(
pll
.
clkin
,
self
.
cd_sys
.
clk
)
platform
.
add_false_path_constraints
(
self
.
cd_sys
.
clk
,
pll
.
clkin
)
# Ignore sys_clk to pll.clkin path created by SoC's rst.
self
.
specials
+=
[
Instance
(
"BUFGCE_DIV"
,
name
=
"main_bufgce_div"
,
...
...
litex_boards/targets/zybo_z7.py
View file @
d73bd2f7
...
...
@@ -40,7 +40,7 @@ class _CRG(Module):
self
.
comb
+=
pll
.
reset
.
eq
(
self
.
rst
)
pll
.
register_clkin
(
platform
.
request
(
"clk125"
),
125e6
)
pll
.
create_clkout
(
self
.
cd_sys
,
sys_clk_freq
)
platform
.
add_false_path_constraints
(
pll
.
clkin
,
self
.
cd_sys
.
clk
)
platform
.
add_false_path_constraints
(
self
.
cd_sys
.
clk
,
pll
.
clkin
)
# Ignore sys_clk to pll.clkin path created by SoC's rst.
# BaseSoC ------------------------------------------------------------------------------------------
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment