Commit d42af3ea authored by Florent Kermarrec's avatar Florent Kermarrec

targets: add --sys-clk-freq support to all targets.

parent 72afb953
...@@ -145,17 +145,20 @@ def main(): ...@@ -145,17 +145,20 @@ def main():
soc_sdram_args(parser) soc_sdram_args(parser)
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
parser.add_argument("--ethernet-phy", default="rgmii", help="Select Ethernet PHY: rgmii (default) or 1000basex") parser.add_argument("--ethernet-phy", default="rgmii", help="Select Ethernet PHY: rgmii (default) or 1000basex")
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") parser.add_argument("--driver", action="store_true", help="Generate PCIe driver")
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC( soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet, with_ethernet = args.with_ethernet,
ethernet_phy = args.ethernet_phy, ethernet_phy = args.ethernet_phy,
with_pcie = args.with_pcie, with_pcie = args.with_pcie,
**soc_sdram_argdict(args)) **soc_sdram_argdict(args)
)
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build) builder.build(run=args.build)
......
...@@ -72,9 +72,8 @@ class CRG(Module): ...@@ -72,9 +72,8 @@ class CRG(Module):
# BaseSoC ----------------------------------------------------------------------------------------- # BaseSoC -----------------------------------------------------------------------------------------
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
def __init__(self, with_pcie=False, **kwargs): def __init__(self, sys_clk_freq=int(100e6), with_pcie=False, **kwargs):
platform = acorn_cle_215.Platform() platform = acorn_cle_215.Platform()
sys_clk_freq = int(100e6)
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, SoCCore.__init__(self, platform, sys_clk_freq,
...@@ -124,6 +123,7 @@ def main(): ...@@ -124,6 +123,7 @@ def main():
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--flash", action="store_true", help="Flash bitstream") parser.add_argument("--flash", action="store_true", help="Flash bitstream")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") parser.add_argument("--driver", action="store_true", help="Generate PCIe driver")
parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support (requires SDCard adapter on P2)") parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support (requires SDCard adapter on P2)")
...@@ -131,7 +131,11 @@ def main(): ...@@ -131,7 +131,11 @@ def main():
soc_sdram_args(parser) soc_sdram_args(parser)
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC(with_pcie = args.with_pcie, **soc_sdram_argdict(args)) soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_pcie = args.with_pcie,
**soc_sdram_argdict(args)
)
if args.with_spi_sdcard: if args.with_spi_sdcard:
soc.add_spi_sdcard() soc.add_spi_sdcard()
......
...@@ -56,9 +56,8 @@ class CRG(Module): ...@@ -56,9 +56,8 @@ class CRG(Module):
# BaseSoC ----------------------------------------------------------------------------------------- # BaseSoC -----------------------------------------------------------------------------------------
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
def __init__(self, with_pcie=False, **kwargs): def __init__(self, sys_clk_freq=int(100e6), with_pcie=False, **kwargs):
platform = aller.Platform() platform = aller.Platform()
sys_clk_freq = int(100e6)
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, SoCCore.__init__(self, platform, sys_clk_freq,
...@@ -105,15 +104,20 @@ class BaseSoC(SoCCore): ...@@ -105,15 +104,20 @@ class BaseSoC(SoCCore):
def main(): def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Aller") parser = argparse.ArgumentParser(description="LiteX SoC on Aller")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--driver", action="store_true", help="Generate LitePCIe driver") parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
parser.add_argument("--driver", action="store_true", help="Generate LitePCIe driver")
builder_args(parser) builder_args(parser)
soc_sdram_args(parser) soc_sdram_args(parser)
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC(with_pcie=args.with_pcie, **soc_sdram_argdict(args)) soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_pcie = args.with_pcie,
**soc_sdram_argdict(args)
)
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build) builder.build(run=args.build)
......
...@@ -110,15 +110,20 @@ class BaseSoC(SoCCore): ...@@ -110,15 +110,20 @@ class BaseSoC(SoCCore):
def main(): def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Alveo U250") parser = argparse.ArgumentParser(description="LiteX SoC on Alveo U250")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver")
builder_args(parser) builder_args(parser)
soc_sdram_args(parser) soc_sdram_args(parser)
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC(with_pcie=args.with_pcie, **soc_sdram_argdict(args)) soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_pcie = args.with_pcie,
**soc_sdram_argdict(args)
)
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build) builder.build(run=args.build)
......
...@@ -106,6 +106,7 @@ def main(): ...@@ -106,6 +106,7 @@ def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7") parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support") parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
...@@ -116,8 +117,12 @@ def main(): ...@@ -116,8 +117,12 @@ def main():
args = parser.parse_args() args = parser.parse_args()
assert not (args.with_ethernet and args.with_etherbone) assert not (args.with_ethernet and args.with_etherbone)
soc = BaseSoC(with_ethernet=args.with_ethernet, with_etherbone=args.with_etherbone, soc = BaseSoC(
**soc_sdram_argdict(args)) sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
**soc_sdram_argdict(args)
)
assert not (args.with_spi_sdcard and args.with_sdcard) assert not (args.with_spi_sdcard and args.with_sdcard)
soc.platform.add_extension(arty._sdcard_pmod_io) soc.platform.add_extension(arty._sdcard_pmod_io)
if args.with_spi_sdcard: if args.with_spi_sdcard:
......
...@@ -90,14 +90,18 @@ class BaseSoC(SoCCore): ...@@ -90,14 +90,18 @@ class BaseSoC(SoCCore):
def main(): def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Arty S7") parser = argparse.ArgumentParser(description="LiteX SoC on Arty S7")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
builder_args(parser) builder_args(parser)
soc_sdram_args(parser) soc_sdram_args(parser)
vivado_build_args(parser) vivado_build_args(parser)
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC(**soc_sdram_argdict(args)) soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
**soc_sdram_argdict(args)
)
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build(**vivado_build_argdict(args), run=args.build) builder.build(**vivado_build_argdict(args), run=args.build)
......
...@@ -109,12 +109,17 @@ def main(): ...@@ -109,12 +109,17 @@ def main():
parser = argparse.ArgumentParser(description="LiteX SoC on C10 LP RefKit") parser = argparse.ArgumentParser(description="LiteX SoC on C10 LP RefKit")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq", default=500e6, help="System clock frequency (default: 50MHz)")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
builder_args(parser) builder_args(parser)
soc_sdram_args(parser) soc_sdram_args(parser)
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args)) soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet,
**soc_sdram_argdict(args)
)
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build) builder.build(run=args.build)
......
...@@ -113,15 +113,20 @@ class BaseSoC(SoCCore): ...@@ -113,15 +113,20 @@ class BaseSoC(SoCCore):
def main(): def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Cam Link 4K") parser = argparse.ArgumentParser(description="LiteX SoC on Cam Link 4K")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain: trellis (default) or diamond") parser.add_argument("--sys-clk-freq", default=81e6, help="System clock frequency (default: 81MHz)")
parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain: trellis (default) or diamond")
builder_args(parser) builder_args(parser)
soc_sdram_args(parser) soc_sdram_args(parser)
trellis_args(parser) trellis_args(parser)
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC(toolchain=args.toolchain, **soc_sdram_argdict(args)) soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
toolchain = args.toolchain,
**soc_sdram_argdict(args)
)
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {} builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs, run=args.build) builder.build(**builder_kargs, run=args.build)
......
...@@ -118,7 +118,7 @@ class _CRG(Module): ...@@ -118,7 +118,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
def __init__(self, board, revision, with_ethernet=False, with_etherbone=False, eth_phy=0, sys_clk_freq=60e6, use_internal_osc=False, sdram_rate="1:1", **kwargs): def __init__(self, board, revision, sys_clk_freq=60e6, with_ethernet=False, with_etherbone=False, eth_phy=0, use_internal_osc=False, sdram_rate="1:1", **kwargs):
board = board.lower() board = board.lower()
assert board in ["5a-75b", "5a-75e"] assert board in ["5a-75b", "5a-75e"]
if board == "5a-75b": if board == "5a-75b":
...@@ -179,10 +179,10 @@ def main(): ...@@ -179,10 +179,10 @@ def main():
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--board", default="5a-75b", help="Board type: 5a-75b (default) or 5a-75e") parser.add_argument("--board", default="5a-75b", help="Board type: 5a-75b (default) or 5a-75e")
parser.add_argument("--revision", default="7.0", type=str, help="Board revision: 7.0 (default), 6.0 or 6.1") parser.add_argument("--revision", default="7.0", type=str, help="Board revision: 7.0 (default), 6.0 or 6.1")
parser.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency (default: 60MHz)")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY: 0 (default) or 1") parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY: 0 (default) or 1")
parser.add_argument("--sys-clk-freq", default=60e6, type=float, help="System clock frequency (default: 60MHz)")
parser.add_argument("--use-internal-osc", action="store_true", help="Use internal oscillator") parser.add_argument("--use-internal-osc", action="store_true", help="Use internal oscillator")
parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate") parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate")
builder_args(parser) builder_args(parser)
...@@ -192,13 +192,14 @@ def main(): ...@@ -192,13 +192,14 @@ def main():
assert not (args.with_ethernet and args.with_etherbone) assert not (args.with_ethernet and args.with_etherbone)
soc = BaseSoC(board=args.board, revision=args.revision, soc = BaseSoC(board=args.board, revision=args.revision,
sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet, with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone, with_etherbone = args.with_etherbone,
eth_phy = args.eth_phy, eth_phy = args.eth_phy,
sys_clk_freq = args.sys_clk_freq,
use_internal_osc = args.use_internal_osc, use_internal_osc = args.use_internal_osc,
sdram_rate = args.sdram_rate, sdram_rate = args.sdram_rate,
**soc_core_argdict(args)) **soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build(**trellis_argdict(args), run=args.build) builder.build(**trellis_argdict(args), run=args.build)
......
...@@ -66,7 +66,7 @@ class BaseSoC(SoCCore): ...@@ -66,7 +66,7 @@ class BaseSoC(SoCCore):
"sram": 0x40000000, "sram": 0x40000000,
"csr": 0xf0000000, "csr": 0xf0000000,
} }
def __init__(self, sys_clk_freq, **kwargs): def __init__(self, sys_clk_freq=int(75e6), **kwargs):
platform = crosslink_nx_evn.Platform() platform = crosslink_nx_evn.Platform()
platform.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=SERIAL}}") platform.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=SERIAL}}")
...@@ -78,8 +78,8 @@ class BaseSoC(SoCCore): ...@@ -78,8 +78,8 @@ class BaseSoC(SoCCore):
# SoCCore -----------------------------------------_---------------------------------------- # SoCCore -----------------------------------------_----------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Crosslink-NX Evaluation Board", ident = "LiteX SoC on Crosslink-NX Evaluation Board",
ident_version = True, ident_version = True,
**kwargs) **kwargs)
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
...@@ -110,7 +110,10 @@ def main(): ...@@ -110,7 +110,10 @@ def main():
soc_core_args(parser) soc_core_args(parser)
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), **soc_core_argdict(args)) soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder_kargs = {} builder_kargs = {}
builder.build(**builder_kargs, run=args.build) builder.build(**builder_kargs, run=args.build)
......
...@@ -67,7 +67,7 @@ class BaseSoC(SoCCore): ...@@ -67,7 +67,7 @@ class BaseSoC(SoCCore):
"sram": 0x40000000, "sram": 0x40000000,
"csr": 0xf0000000, "csr": 0xf0000000,
} }
def __init__(self, sys_clk_freq, hyperram="none", **kwargs): def __init__(self, sys_clk_freq=int(75e6), hyperram="none", **kwargs):
platform = crosslink_nx_vip.Platform() platform = crosslink_nx_vip.Platform()
platform.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=SERIAL}}") platform.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=SERIAL}}")
...@@ -108,14 +108,18 @@ def main(): ...@@ -108,14 +108,18 @@ def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Crosslink-NX VIP Board") parser = argparse.ArgumentParser(description="LiteX SoC on Crosslink-NX VIP Board")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--with-hyperram", default="none", help="Enable use of HyperRAM chip: none (default), 0 or 1")
parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)") parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)")
parser.add_argument("--with-hyperram", default="none", help="Enable use of HyperRAM chip: none (default), 0 or 1")
parser.add_argument("--prog-target", default="direct", help="Programming Target: direct (default) or flash") parser.add_argument("--prog-target", default="direct", help="Programming Target: direct (default) or flash")
builder_args(parser) builder_args(parser)
soc_core_args(parser) soc_core_args(parser)
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), hyperram=args.with_hyperram, **soc_core_argdict(args)) soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
hyperram = args.with_hyperram,
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder_kargs = {} builder_kargs = {}
builder.build(**builder_kargs, run=args.build) builder.build(**builder_kargs, run=args.build)
......
...@@ -96,14 +96,19 @@ class BaseSoC(SoCCore): ...@@ -96,14 +96,19 @@ class BaseSoC(SoCCore):
def main(): def main():
parser = argparse.ArgumentParser(description="LiteX SoC on DE0-Nano") parser = argparse.ArgumentParser(description="LiteX SoC on DE0-Nano")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate") parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate")
builder_args(parser) builder_args(parser)
soc_sdram_args(parser) soc_sdram_args(parser)
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC(sdram_rate=args.sdram_rate, **soc_sdram_argdict(args)) soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
sdram_rate = args.sdram_rate,
**soc_sdram_argdict(args)
)
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build) builder.build(run=args.build)
......
...@@ -104,14 +104,19 @@ class BaseSoC(SoCCore): ...@@ -104,14 +104,19 @@ class BaseSoC(SoCCore):
def main(): def main():
parser = argparse.ArgumentParser(description="LiteX SoC on DE10-Lite") parser = argparse.ArgumentParser(description="LiteX SoC on DE10-Lite")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--with-vga", action="store_true", help="Enable VGA support") parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
parser.add_argument("--with-vga", action="store_true", help="Enable VGA support")
builder_args(parser) builder_args(parser)
soc_sdram_args(parser) soc_sdram_args(parser)
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC(with_vga=args.with_vga, **soc_sdram_argdict(args)) soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_vga = args.with_vga,
**soc_sdram_argdict(args)
)
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build) builder.build(run=args.build)
......
...@@ -117,17 +117,21 @@ def main(): ...@@ -117,17 +117,21 @@ def main():
parser = argparse.ArgumentParser(description="LiteX SoC on DE10-Nano") parser = argparse.ArgumentParser(description="LiteX SoC on DE10-Nano")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
parser.add_argument("--with-mister-sdram", action="store_true", help="Enable SDRAM with MiSTer expansion board") parser.add_argument("--with-mister-sdram", action="store_true", help="Enable SDRAM with MiSTer expansion board")
parser.add_argument("--with-mister-vga", action="store_true", help="Enable VGA with Mister expansion board") parser.add_argument("--with-mister-vga", action="store_true", help="Enable VGA with Mister expansion board")
parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate") parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate")
args = parser.parse_args() args = parser.parse_args()
builder_args(parser) builder_args(parser)
soc_sdram_args(parser) soc_sdram_args(parser)
soc = BaseSoC( soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_mister_sdram = args.with_mister_sdram, with_mister_sdram = args.with_mister_sdram,
with_mister_vga = args.with_mister_vga, with_mister_vga = args.with_mister_vga,
sdram_rate = args.sdram_rate, sdram_rate = args.sdram_rate,
**soc_sdram_argdict(args)) **soc_sdram_argdict(args)
)
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build) builder.build(run=args.build)
......
...@@ -79,13 +79,17 @@ class BaseSoC(SoCCore): ...@@ -79,13 +79,17 @@ class BaseSoC(SoCCore):
def main(): def main():
parser = argparse.ArgumentParser(description="LiteX SoC on DE1-SoC") parser = argparse.ArgumentParser(description="LiteX SoC on DE1-SoC")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
builder_args(parser) builder_args(parser)
soc_sdram_args(parser) soc_sdram_args(parser)
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC(**soc_sdram_argdict(args)) soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
**soc_sdram_argdict(args)
)
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build) builder.build(run=args.build)
......
...@@ -79,13 +79,17 @@ class BaseSoC(SoCCore): ...@@ -79,13 +79,17 @@ class BaseSoC(SoCCore):
def main(): def main():
parser = argparse.ArgumentParser(description="LiteX SoC on DE2-115") parser = argparse.ArgumentParser(description="LiteX SoC on DE2-115")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
builder_args(parser) builder_args(parser)
soc_sdram_args(parser) soc_sdram_args(parser)
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC(**soc_sdram_argdict(args)) soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
**soc_sdram_argdict(args)
)
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build) builder.build(run=args.build)
......
...@@ -127,6 +127,7 @@ def main(): ...@@ -127,6 +127,7 @@ def main():
parser = argparse.ArgumentParser(description="LiteX SoC on ECPIX-5") parser = argparse.ArgumentParser(description="LiteX SoC on ECPIX-5")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)")
parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
builder_args(parser) builder_args(parser)
...@@ -134,7 +135,11 @@ def main(): ...@@ -134,7 +135,11 @@ def main():
trellis_args(parser) trellis_args(parser)
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_core_argdict(args)) soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet,
**soc_core_argdict(args)
)
if args.with_sdcard: if args.with_sdcard:
soc.add_sdcard() soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
......
...@@ -102,15 +102,20 @@ class BaseSoC(SoCCore): ...@@ -102,15 +102,20 @@ class BaseSoC(SoCCore):
def main(): def main():
parser = argparse.ArgumentParser(description="LiteX SoC on FK33") parser = argparse.ArgumentParser(description="LiteX SoC on FK33")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver")
builder_args(parser)