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Kestrel Collaboration
Kestrel LiteX
litex-boards
Commits
d0ca1bef
Commit
d0ca1bef
authored
Jul 24, 2020
by
Florent Kermarrec
Browse files
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Plain Diff
targets/de10nano/minispartan6: simplify HalfRate support, rename argument to sdram_rate.
parent
9730c6f7
Changes
2
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Showing
2 changed files
with
35 additions
and
39 deletions
+35
-39
litex_boards/targets/de10nano.py
litex_boards/targets/de10nano.py
+13
-17
litex_boards/targets/minispartan6.py
litex_boards/targets/minispartan6.py
+22
-22
No files found.
litex_boards/targets/de10nano.py
View file @
d0ca1bef
...
...
@@ -28,14 +28,15 @@ from litevideo.terminal.core import Terminal
# CRG ----------------------------------------------------------------------------------------------
class
_CRG
(
Module
):
def
__init__
(
self
,
platform
,
sys_clk_freq
,
with_sdram
=
False
,
sdram_
sys2x
=
False
):
def
__init__
(
self
,
platform
,
sys_clk_freq
,
with_sdram
=
False
,
sdram_
rate
=
"1:1"
):
self
.
clock_domains
.
cd_sys
=
ClockDomain
()
if
sdram_
sys2x
:
self
.
clock_domains
.
cd_sys2x
=
ClockDomain
()
if
sdram_
rate
==
"1:2"
:
self
.
clock_domains
.
cd_sys2x
=
ClockDomain
()
self
.
clock_domains
.
cd_sys2x_ps
=
ClockDomain
(
reset_less
=
True
)
else
:
self
.
clock_domains
.
cd_sys_ps
=
ClockDomain
(
reset_less
=
True
)
self
.
clock_domains
.
cd_vga
=
ClockDomain
(
reset_less
=
True
)
# # #
# Clk / Rst
...
...
@@ -45,8 +46,8 @@ class _CRG(Module):
self
.
submodules
.
pll
=
pll
=
CycloneVPLL
(
speedgrade
=
"-I7"
)
pll
.
register_clkin
(
clk50
,
50e6
)
pll
.
create_clkout
(
self
.
cd_sys
,
sys_clk_freq
)
if
sdram_
sys2x
:
pll
.
create_clkout
(
self
.
cd_sys2x
,
2
*
sys_clk_freq
)
if
sdram_
rate
==
"1:2"
:
pll
.
create_clkout
(
self
.
cd_sys2x
,
2
*
sys_clk_freq
)
pll
.
create_clkout
(
self
.
cd_sys2x_ps
,
2
*
sys_clk_freq
,
phase
=
90
)
else
:
pll
.
create_clkout
(
self
.
cd_sys_ps
,
sys_clk_freq
,
phase
=
90
)
...
...
@@ -54,13 +55,13 @@ class _CRG(Module):
# SDRAM clock
if
with_sdram
:
sdram_clk
=
ClockSignal
(
"sys2x_ps"
if
sdram_
sys2x
else
"sys_ps"
)
sdram_clk
=
ClockSignal
(
"sys2x_ps"
if
sdram_
rate
==
"1:2"
else
"sys_ps"
)
self
.
specials
+=
DDROutput
(
1
,
0
,
platform
.
request
(
"sdram_clock"
),
sdram_clk
)
# BaseSoC ------------------------------------------------------------------------------------------
class
BaseSoC
(
SoCCore
):
def
__init__
(
self
,
sys_clk_freq
=
int
(
50e6
),
with_mister_sdram
=
True
,
with_mister_vga
=
False
,
sdram_
sys2x
=
False
,
**
kwargs
):
def
__init__
(
self
,
sys_clk_freq
=
int
(
50e6
),
with_mister_sdram
=
True
,
with_mister_vga
=
False
,
sdram_
rate
=
"1:1"
,
**
kwargs
):
platform
=
de10nano
.
Platform
()
# SoCCore ----------------------------------------------------------------------------------
...
...
@@ -70,19 +71,14 @@ class BaseSoC(SoCCore):
**
kwargs
)
# CRG --------------------------------------------------------------------------------------
self
.
submodules
.
crg
=
_CRG
(
platform
,
sys_clk_freq
,
with_sdram
=
with_mister_sdram
,
sdram_
sys2x
=
sdram_sys2x
)
self
.
submodules
.
crg
=
_CRG
(
platform
,
sys_clk_freq
,
with_sdram
=
with_mister_sdram
,
sdram_
rate
=
sdram_rate
)
# SDR SDRAM --------------------------------------------------------------------------------
if
with_mister_sdram
and
not
self
.
integrated_main_ram_size
:
if
sdram_sys2x
:
self
.
submodules
.
sdrphy
=
HalfRateGENSDRPHY
(
platform
.
request
(
"sdram"
))
rate
=
"1:2"
else
:
self
.
submodules
.
sdrphy
=
GENSDRPHY
(
platform
.
request
(
"sdram"
))
rate
=
"1:1"
sdrphy_cls
=
HalfRateGENSDRPHY
if
sdram_rate
==
"1:2"
else
GENSDRPHY
self
.
add_sdram
(
"sdram"
,
phy
=
self
.
sdrphy
,
module
=
AS4C32M16
(
sys_clk_freq
,
rate
),
module
=
AS4C32M16
(
sys_clk_freq
,
sdram_
rate
),
origin
=
self
.
mem_map
[
"main_ram"
],
size
=
kwargs
.
get
(
"max_sdram_size"
,
0x40000000
),
l2_cache_size
=
kwargs
.
get
(
"l2_size"
,
8192
),
...
...
@@ -119,12 +115,12 @@ def main():
soc_sdram_args
(
parser
)
parser
.
add_argument
(
"--with-mister-sdram"
,
action
=
"store_true"
,
help
=
"Enable SDRAM with MiSTer expansion board"
)
parser
.
add_argument
(
"--with-mister-vga"
,
action
=
"store_true"
,
help
=
"Enable VGA with Mister expansion board"
)
parser
.
add_argument
(
"--sdram-
sys2x"
,
action
=
"store_true"
,
help
=
"Use double frequency for SDRAM PHY
"
)
parser
.
add_argument
(
"--sdram-
rate"
,
default
=
"1:1"
,
help
=
"SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate
"
)
args
=
parser
.
parse_args
()
soc
=
BaseSoC
(
with_mister_sdram
=
args
.
with_mister_sdram
,
with_mister_vga
=
args
.
with_mister_vga
,
sdram_
sys2x
=
args
.
sdram_sys2x
,
sdram_
rate
=
args
.
sdram_rate
,
**
soc_sdram_argdict
(
args
))
builder
=
Builder
(
soc
,
**
builder_argdict
(
args
))
builder
.
build
(
run
=
args
.
build
)
...
...
litex_boards/targets/minispartan6.py
View file @
d0ca1bef
...
...
@@ -16,7 +16,7 @@ from litex.build.io import DDROutput
from
litex_boards.platforms
import
minispartan6
from
litex.soc.cores.clock
import
*
from
litex.soc.cores.clock
import
S6PLL
from
litex.soc.integration.soc_core
import
*
from
litex.soc.integration.soc_sdram
import
*
from
litex.soc.integration.builder
import
*
...
...
@@ -28,33 +28,37 @@ from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
# CRG ----------------------------------------------------------------------------------------------
class
_CRG
(
Module
):
def
__init__
(
self
,
platform
,
clk_freq
,
sdram_sys2x
=
False
):
def
__init__
(
self
,
platform
,
sys_clk_freq
,
sdram_rate
=
"1:1"
):
self
.
clock_domains
.
cd_sys
=
ClockDomain
()
if
sdram_
sys2x
:
self
.
clock_domains
.
cd_sys2x
=
ClockDomain
()
if
sdram_
rate
==
"1:2"
:
self
.
clock_domains
.
cd_sys2x
=
ClockDomain
()
self
.
clock_domains
.
cd_sys2x_ps
=
ClockDomain
(
reset_less
=
True
)
else
:
self
.
clock_domains
.
cd_sys_ps
=
ClockDomain
(
reset_less
=
True
)
# # #
# Clk / Rst
clk32
=
platform
.
request
(
"clk32"
)
# PLL
self
.
submodules
.
pll
=
pll
=
S6PLL
(
speedgrade
=-
1
)
pll
.
register_clkin
(
platform
.
request
(
"clk32"
)
,
32e6
)
pll
.
create_clkout
(
self
.
cd_sys
,
clk_freq
)
if
sdram_
sys2x
:
pll
.
create_clkout
(
self
.
cd_sys2x
,
2
*
clk_freq
)
pll
.
create_clkout
(
self
.
cd_sys2x_ps
,
2
*
clk_freq
,
phase
=
90
)
pll
.
register_clkin
(
clk32
,
32e6
)
pll
.
create_clkout
(
self
.
cd_sys
,
sys_
clk_freq
)
if
sdram_
rate
==
"1:2"
:
pll
.
create_clkout
(
self
.
cd_sys2x
,
2
*
sys_
clk_freq
)
pll
.
create_clkout
(
self
.
cd_sys2x_ps
,
2
*
sys_
clk_freq
,
phase
=
90
)
else
:
pll
.
create_clkout
(
self
.
cd_sys_ps
,
clk_freq
,
phase
=
90
)
pll
.
create_clkout
(
self
.
cd_sys_ps
,
sys_
clk_freq
,
phase
=
90
)
# SDRAM clock
sdram_clk
=
ClockSignal
(
"sys2x_ps"
if
sdram_
sys2x
else
"sys_ps"
)
sdram_clk
=
ClockSignal
(
"sys2x_ps"
if
sdram_
rate
==
"1:2"
else
"sys_ps"
)
self
.
specials
+=
DDROutput
(
1
,
0
,
platform
.
request
(
"sdram_clock"
),
sdram_clk
)
# BaseSoC ------------------------------------------------------------------------------------------
class
BaseSoC
(
SoCCore
):
def
__init__
(
self
,
sys_clk_freq
=
int
(
80e6
),
sdram_
sys2x
=
False
,
**
kwargs
):
def
__init__
(
self
,
sys_clk_freq
=
int
(
80e6
),
sdram_
rate
=
"1:1"
,
**
kwargs
):
platform
=
minispartan6
.
Platform
()
# SoCCore ----------------------------------------------------------------------------------
...
...
@@ -64,19 +68,15 @@ class BaseSoC(SoCCore):
**
kwargs
)
# CRG --------------------------------------------------------------------------------------
self
.
submodules
.
crg
=
_CRG
(
platform
,
sys_clk_freq
,
sdram_
sys2x
=
sdram_sys2x
)
self
.
submodules
.
crg
=
_CRG
(
platform
,
sys_clk_freq
,
sdram_
rate
=
sdram_rate
)
# SDR SDRAM --------------------------------------------------------------------------------
if
not
self
.
integrated_main_ram_size
:
if
sdram_sys2x
:
self
.
submodules
.
sdrphy
=
HalfRateGENSDRPHY
(
platform
.
request
(
"sdram"
))
rate
=
"1:2"
else
:
self
.
submodules
.
sdrphy
=
GENSDRPHY
(
platform
.
request
(
"sdram"
))
rate
=
"1:1"
sdrphy_cls
=
HalfRateGENSDRPHY
if
sdram_rate
==
"1:2"
else
GENSDRPHY
self
.
submodules
.
sdrphy
=
sdrphy_cls
(
platform
.
request
(
"sdram"
))
self
.
add_sdram
(
"sdram"
,
phy
=
self
.
sdrphy
,
module
=
AS4C16M16
(
sys_clk_freq
,
rate
),
module
=
AS4C16M16
(
sys_clk_freq
,
sdram_
rate
),
origin
=
self
.
mem_map
[
"main_ram"
],
size
=
kwargs
.
get
(
"max_sdram_size"
,
0x40000000
),
l2_cache_size
=
kwargs
.
get
(
"l2_size"
,
8192
),
...
...
@@ -96,12 +96,12 @@ def main():
parser
=
argparse
.
ArgumentParser
(
description
=
"LiteX SoC on MiniSpartan6"
)
parser
.
add_argument
(
"--build"
,
action
=
"store_true"
,
help
=
"Build bitstream"
)
parser
.
add_argument
(
"--load"
,
action
=
"store_true"
,
help
=
"Load bitstream"
)
parser
.
add_argument
(
"--sdram-
sys2x"
,
action
=
"store_true"
,
help
=
"Use double frequency for SDRAM PHY
"
)
parser
.
add_argument
(
"--sdram-
rate"
,
default
=
"1:1"
,
help
=
"SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate
"
)
builder_args
(
parser
)
soc_sdram_args
(
parser
)
args
=
parser
.
parse_args
()
soc
=
BaseSoC
(
sdram_
sys2x
=
args
.
sdram_sys2x
,
**
soc_sdram_argdict
(
args
))
soc
=
BaseSoC
(
sdram_
rate
=
args
.
sdram_rate
,
**
soc_sdram_argdict
(
args
))
builder
=
Builder
(
soc
,
**
builder_argdict
(
args
))
builder
.
build
(
run
=
args
.
build
)
...
...
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