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Kestrel Collaboration
Kestrel LiteX
litex-boards
Commits
ce38cff4
Commit
ce38cff4
authored
Nov 20, 2020
by
Jędrzej Boczar
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mercury_xu5: reduce cmd_latency to fix problems with DRAM leveling
parent
a2f3add2
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litex_boards/targets/mercury_xu5.py
litex_boards/targets/mercury_xu5.py
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litex_boards/targets/mercury_xu5.py
View file @
ce38cff4
...
@@ -73,7 +73,8 @@ class BaseSoC(SoCCore):
...
@@ -73,7 +73,8 @@ class BaseSoC(SoCCore):
self
.
submodules
.
ddrphy
=
usddrphy
.
USPDDRPHY
(
platform
.
request
(
"ddram"
),
self
.
submodules
.
ddrphy
=
usddrphy
.
USPDDRPHY
(
platform
.
request
(
"ddram"
),
memtype
=
"DDR4"
,
memtype
=
"DDR4"
,
sys_clk_freq
=
sys_clk_freq
,
sys_clk_freq
=
sys_clk_freq
,
iodelay_clk_freq
=
500e6
)
iodelay_clk_freq
=
500e6
,
cmd_latency
=
0
)
self
.
add_csr
(
"ddrphy"
)
self
.
add_csr
(
"ddrphy"
)
self
.
add_sdram
(
"sdram"
,
self
.
add_sdram
(
"sdram"
,
phy
=
self
.
ddrphy
,
phy
=
self
.
ddrphy
,
...
...
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