Update official Kestrel development kit target / platform files

parent d74d3539
......@@ -32,15 +32,15 @@ Building the Kestrel BMC for the ECP-5 FPGA on the Versa board is quite straight
Please see the [Quick Start Guide](https://gitlab.raptorengineering.com/kestrel-collaboration/kestrel-litex/litex/-/wikis/Quick-Start) for setup instructions applicable to the standard Raptor development environment on POWER9. After the subrepositories are set up, simply run:
cd kestrel/litex/litex-boards/litex_boards/targets
./versa_ecp5.py --device=LFE5UM --cpu-type=microwatt --cpu-variant=standard+ghdl+irq --with-ethernet --build --nextpnr-seed 1
./kestrel_versa_ecp5.py --device=LFE5UM --cpu-type=microwatt --cpu-variant=standard+ghdl+irq --with-ethernet --build --nextpnr-seed 1
# Updating the bitstream with new firmware
The bitstream is automatically stuffed with valid ROM contents, however, if a developer wishes to update the rom, the following sequence can be used:
cd kestrel/litex/litex-boards/litex_boards/targets/build/versa_ecp5/gateware
ecpbram -i versa_ecp5.config -o versa_ecp5_stuffed.config -f rom.init -t rom_data.init
ecppack versa_ecp5_stuffed.config --svf versa_ecp5.svf --bit versa_ecp5.bit --bootaddr 0
cd kestrel/litex/litex-boards/litex_boards/targets/build/kestrel_versa_ecp5/gateware
ecpbram -i kestrel_versa_ecp5.config -o kestrel_versa_ecp5_stuffed.config -f rom.init -t rom_data.init
ecppack kestrel_versa_ecp5_stuffed.config --svf kestrel_versa_ecp5.svf --bit kestrel_versa_ecp5.bit --bootaddr 0
# How to connect
......@@ -78,7 +78,7 @@ In addition, the ASpeed BMC will need to be deactivated. This is slightly more
## All hosts
Most, if not all, mainboards will require some form of storage for the bootloader and platform firmware. Kestrel contains a high-speed SPI/QSPI master that can be used to attach any standard SPI Flash device. We recommend that all wires be kept as short as possible between the Versa board and the external SPI device to minimize interference and maximize transfer rates.
We strongly recommend you reference the pin configuration file at litex-boards/litex_boards/platforms/versa_ecp5.py when attaching any devices or external mainboards to the Versa board. This file contains the pin information that will, in conjunction with the Versa board schematics, allow correct wiring of the ECP5 to any attached hardware.
We strongly recommend you reference the pin configuration file at litex-boards/litex_boards/platforms/kestrel_versa_ecp5.py when attaching any devices or external mainboards to the Versa board. This file contains the pin information that will, in conjunction with the Versa board schematics, allow correct wiring of the ECP5 to any attached hardware.
# How to use
......@@ -97,7 +97,7 @@ The recommended test setup is two console windows, one running the LiteX termina
and the other running the OpenOCD programming tool:
cd kestrel/litex/litex-boards/litex_boards/targets
openocd --log_output openocd.log 3 -f "/usr/share/trellis/misc/openocd/ecp5-versa.cfg" -c "transport select jtag; init; svf build/versa_ecp5/gateware/versa_ecp5.svf; exit"
openocd --log_output openocd.log -f "/usr/share/trellis/misc/openocd/ecp5-versa.cfg" -c "transport select jtag; init; svf build/kestrel_versa_ecp5/gateware/kestrel_versa_ecp5.svf; exit"
When it is desired to recompile the firmware and re-upload, exit the LiteX terminal with a rapid `Ctrl+C Ctrl+C`, re-run make in the firmware directory, and then restart the LiteX terminal. From there, you may either us the `reboot` command at the BMC terminal, or re-run OpenOCD to reset all hardware inside the FPGA with a new bistream load.
......
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......@@ -18,7 +18,7 @@ _io = [
("rst_n", 0, Pins("T1"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("E6"), IOStandard("LVCMOS33")),
("user_led", 0, Pins("E16"), IOStandard("LVCMOS25")),
("user_led", 1, Pins("D17"), IOStandard("LVCMOS25")),
("user_led", 2, Pins("D18"), IOStandard("LVCMOS25")),
("user_led", 3, Pins("E18"), IOStandard("LVCMOS25")),
......@@ -26,20 +26,20 @@ _io = [
("user_led", 5, Pins("F18"), IOStandard("LVCMOS25")),
("user_led", 6, Pins("E17"), IOStandard("LVCMOS25")),
("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")),
("user_leds", 0, Pins("E6 D17 D18 E18 F17 F18 E17 F16"),
IOStandard("LVCMOS33 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25")),
("user_leds", 0, Pins("E16 D17 D18 E18 F17 F18 E17 F16"),
IOStandard("LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25")),
# Switches
("user_dip_btn", 0, Pins("B19"), IOStandard("LVCMOS15")),
("user_dip_btn", 1, Pins("K3"), IOStandard("LVCMOS15")),
("user_dip_btn", 2, Pins("G3"), IOStandard("LVCMOS15")),
("user_dip_btn", 3, Pins("F2"), IOStandard("LVCMOS15")),
("user_dip_btn", 4, Pins("J18"), IOStandard("LVCMOS25")),
("user_dip_btn", 5, Pins("K18"), IOStandard("LVCMOS25")),
("user_dip_btn", 6, Pins("K19"), IOStandard("LVCMOS25")),
("user_dip_btn", 7, Pins("K20"), IOStandard("LVCMOS25")),
# Alphanumeric display
("user_dip_btn", 0, Pins("B19"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")), # Kestrel Versa adapter power button input
("user_dip_btn", 1, Pins("K3"), IOStandard("LVCMOS15"), Misc("PULLMODE=UP")),
("user_dip_btn", 2, Pins("G3"), IOStandard("LVCMOS15"), Misc("PULLMODE=UP")),
("user_dip_btn", 3, Pins("F2"), IOStandard("LVCMOS15"), Misc("PULLMODE=UP")),
("user_dip_btn", 4, Pins("J18"), IOStandard("LVCMOS25"), Misc("PULLMODE=UP")),
("user_dip_btn", 5, Pins("K18"), IOStandard("LVCMOS25"), Misc("PULLMODE=UP")),
("user_dip_btn", 6, Pins("K19"), IOStandard("LVCMOS25"), Misc("PULLMODE=UP")),
("user_dip_btn", 7, Pins("K20"), IOStandard("LVCMOS25"), Misc("PULLMODE=UP")),
# Alphanumeric display / general outputs
("alpha_led", 0, Pins("M20"), IOStandard("LVCMOS25")),
("alpha_led", 1, Pins("L18"), IOStandard("LVCMOS25")),
("alpha_led", 2, Pins("M19"), IOStandard("LVCMOS25")),
......@@ -55,10 +55,10 @@ _io = [
("alpha_led", 12, Pins("R16"), IOStandard("LVCMOS25")),
("alpha_led", 13, Pins("R17"), IOStandard("LVCMOS25")),
("alpha_led", 14, Pins("U1"), IOStandard("LVCMOS33")),
("alpha_led", 15, Pins("T16"), IOStandard("LVCMOS25")), # Not wired on Versa board, but makes GPIO bank 16 bits. Future expansion?
# T16 not wired on Versa board, but makes GPIO bank 16 bits. Future expansion?
("alpha_leds", 0, Pins("M20 L18 M19 L16 L17 M18 N16 M17 N18 P17 N17 P16 R16 R17 U1 T16"),
IOStandard("LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS33 LVCMOS25")),
("alpha_led", 15, Pins("E6"), IOStandard("LVCMOS33")), # Kestrel Versa adapter power LED output
# E6 is Kestrel Versa adapter power LED output
("alpha_leds", 0, Pins("M20 L18 M19 L16 L17 M18 N16 M17 N18 P17 N17 P16 R16 R17 U1 E6"),
IOStandard("LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS33 LVCMOS33")),
# Serial
("serial", 0,
......@@ -236,7 +236,6 @@ _io = [
Subsignal("addrdata", Pins("A9 C10 E14 A14"), Misc("PULLMODE=UP")),
Subsignal("serirq", Pins("E12"), Misc("PULLMODE=UP")),
Subsignal("clk", Pins("B12"), Misc("PULLMODE=NONE")), # Must be PCLK *not* GR_PCLK or (even worse) a general logic I/O! Pullup NONE helps minimize clock distortion / clock failure on heavily loaded clock lines...
# FIXME meklort adapter board v1 has the clock on a standard input, not a PCLK! Connected to B12 with bodge wire.
IOStandard("LVCMOS33"),
Misc("SLEWRATE=SLOW"),
Misc("DRIVE=16"),
......@@ -246,11 +245,11 @@ _io = [
Subsignal("pwm1", Pins("E7"), IOStandard("LVCMOS33")),
Subsignal("pwm2", Pins("B11"), IOStandard("LVCMOS33")),
Subsignal("pwm3", Pins("E9"), IOStandard("LVCMOS33")),
Subsignal("pwm4", Pins("E16"), IOStandard("LVCMOS25")), # User LED (for debugging)
Subsignal("pwm4", Pins("A18"), IOStandard("LVCMOS33")),
Subsignal("tach1", Pins("B8"), IOStandard("LVCMOS33")),
Subsignal("tach2", Pins("D8"), IOStandard("LVCMOS33")),
Subsignal("tach3", Pins("C7"), IOStandard("LVCMOS33")),
Subsignal("tach4", Pins("H2"), IOStandard("LVCMOS15")), # DIP siwtch (for debugging)
Subsignal("tach4", Pins("B18"), IOStandard("LVCMOS33")),
),
#("debug_port_2", 0,
......
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