From c093d0d0fc13165c74c67a024a66f94764a60594 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 3 Nov 2020 10:48:41 +0100 Subject: [PATCH] platforms: cleanup pass to uniformize comments/separators/orders. --- litex_boards/platforms/ac701.py | 29 ++-- litex_boards/platforms/acorn_cle_215.py | 10 +- litex_boards/platforms/aller.py | 15 +- litex_boards/platforms/alveo_u250.py | 23 +-- litex_boards/platforms/arty.py | 33 ++-- litex_boards/platforms/arty_s7.py | 31 ++-- litex_boards/platforms/avalanche.py | 20 ++- litex_boards/platforms/c10lprefkit.py | 19 +- litex_boards/platforms/camlink_4k.py | 4 + litex_boards/platforms/colorlight_5a_75b.py | 36 ++-- litex_boards/platforms/colorlight_5a_75e.py | 35 ++-- litex_boards/platforms/de0nano.py | 13 +- litex_boards/platforms/de10lite.py | 70 ++++---- litex_boards/platforms/de10nano.py | 19 +- litex_boards/platforms/de1soc.py | 3 + litex_boards/platforms/de2_115.py | 3 + litex_boards/platforms/ecp5_evn.py | 27 +-- litex_boards/platforms/ecpix5.py | 14 +- litex_boards/platforms/fk33.py | 4 + litex_boards/platforms/fomu_evt.py | 8 + litex_boards/platforms/fomu_hacker.py | 6 +- litex_boards/platforms/fomu_pvt.py | 5 + litex_boards/platforms/genesys2.py | 38 ++-- litex_boards/platforms/hadbadge.py | 57 +++--- litex_boards/platforms/icebreaker.py | 17 +- litex_boards/platforms/kc705.py | 181 +++++++++----------- litex_boards/platforms/kcu105.py | 60 ++++--- litex_boards/platforms/kx2.py | 17 +- litex_boards/platforms/linsn_rv901t.py | 11 +- litex_boards/platforms/logicbone.py | 44 +++-- litex_boards/platforms/machxo3.py | 4 + litex_boards/platforms/marblemini.py | 7 +- litex_boards/platforms/mercury_xu5.py | 9 +- litex_boards/platforms/mimas_a7.py | 31 ++-- litex_boards/platforms/minispartan6.py | 52 +++--- litex_boards/platforms/mist.py | 21 ++- litex_boards/platforms/nereid.py | 76 +++----- litex_boards/platforms/netv2.py | 42 ++--- litex_boards/platforms/nexys4ddr.py | 16 +- litex_boards/platforms/nexys_video.py | 19 +- litex_boards/platforms/orangecrab.py | 31 ++-- litex_boards/platforms/pano_logic_g2.py | 18 +- litex_boards/platforms/pipistrello.py | 53 +++--- litex_boards/platforms/sp605.py | 19 +- litex_boards/platforms/tagus.py | 37 ++-- litex_boards/platforms/tec0117.py | 9 +- litex_boards/platforms/tinyfpga_bx.py | 9 +- litex_boards/platforms/trellisboard.py | 58 ++++--- litex_boards/platforms/ulx3s.py | 22 ++- litex_boards/platforms/vc707.py | 62 +++---- litex_boards/platforms/vcu118.py | 7 +- litex_boards/platforms/versa_ecp5.py | 27 ++- litex_boards/platforms/xcu1525.py | 15 +- litex_boards/platforms/zcu104.py | 11 +- litex_boards/platforms/zedboard.py | 54 +++--- litex_boards/platforms/zybo_z7.py | 12 +- litex_boards/targets/logicbone.py | 2 +- 57 files changed, 894 insertions(+), 681 deletions(-) diff --git a/litex_boards/platforms/ac701.py b/litex_boards/platforms/ac701.py index c2d5c4a..1a0f37c 100644 --- a/litex_boards/platforms/ac701.py +++ b/litex_boards/platforms/ac701.py @@ -11,23 +11,24 @@ from litex.build.openocd import OpenOCD # IOs ---------------------------------------------------------------------------------------------- _io = [ - ("user_led", 0, Pins("M26"), IOStandard("LVCMOS33")), - ("user_led", 1, Pins("T24"), IOStandard("LVCMOS33")), - ("user_led", 2, Pins("T25"), IOStandard("LVCMOS33")), - ("user_led", 3, Pins("R26"), IOStandard("LVCMOS33")), - - ("cpu_reset", 0, Pins("U4"), IOStandard("SSTL15")), - + # Clk / Rst ("clk200", 0, Subsignal("p", Pins("R3"), IOStandard("DIFF_SSTL15")), Subsignal("n", Pins("P3"), IOStandard("DIFF_SSTL15")) ), - ("clk156", 0, Subsignal("p", Pins("M21"), IOStandard("LVDS_25")), Subsignal("n", Pins("M22"), IOStandard("LVDS_25")) ), + ("cpu_reset", 0, Pins("U4"), IOStandard("SSTL15")), + + # Leds + ("user_led", 0, Pins("M26"), IOStandard("LVCMOS33")), + ("user_led", 1, Pins("T24"), IOStandard("LVCMOS33")), + ("user_led", 2, Pins("T25"), IOStandard("LVCMOS33")), + ("user_led", 3, Pins("R26"), IOStandard("LVCMOS33")), + # Serial ("serial", 0, Subsignal("cts", Pins("V19")), Subsignal("rts", Pins("W19")), @@ -36,12 +37,12 @@ _io = [ IOStandard("LVCMOS18") ), + # RGMII Ethernet ("eth_clocks", 0, Subsignal("tx", Pins("U22")), Subsignal("rx", Pins("U21")), IOStandard("LVCMOS18") ), - ("eth", 0, Subsignal("rx_ctl", Pins("U14")), Subsignal("rx_data", Pins("U17 V17 V16 V14")), @@ -55,6 +56,7 @@ _io = [ IOStandard("LVCMOS18"), ), + # DDR3 SDRAM ("ddram", 0, Subsignal("a", Pins( "M4 J3 J1 L4 K5 M7 K1 M6", @@ -90,6 +92,7 @@ _io = [ Misc("SLEW=FAST"), ), + # PCIe ("pcie_x1", 0, Subsignal("rst_n", Pins("M20"), IOStandard("LVCMOS25")), Subsignal("clk_p", Pins("F11")), @@ -100,13 +103,13 @@ _io = [ Subsignal("tx_n", Pins("C10")) ), - ("vadj_on_b", 0, Pins("R16"), IOStandard("LVCMOS25")), - + # GTP RefClk ("gtp_refclk", 0, Subsignal("p", Pins("AA13")), Subsignal("n", Pins("AB13")) ), + # SFP ("sfp", 0, Subsignal("txp", Pins("AC10")), Subsignal("txn", Pins("AD10")), @@ -117,6 +120,10 @@ _io = [ ("sfp_mgt_clk_sel1", 0, Pins("C24"), IOStandard("LVCMOS25")), ("sfp_tx_disable_n", 0, Pins("R18"), IOStandard("LVCMOS33")), ("sfp_rx_los", 0, Pins("R23"), IOStandard("LVCMOS33")), + + # Others + ("vadj_on_b", 0, Pins("R16"), IOStandard("LVCMOS25")), + ] # Connectors --------------------------------------------------------------------------------------- diff --git a/litex_boards/platforms/acorn_cle_215.py b/litex_boards/platforms/acorn_cle_215.py index 84586e3..1ddefd7 100644 --- a/litex_boards/platforms/acorn_cle_215.py +++ b/litex_boards/platforms/acorn_cle_215.py @@ -14,19 +14,19 @@ from litex.build.openocd import OpenOCD # IOs ---------------------------------------------------------------------------------------------- _io = [ - # clk / rst + # Clk / Rst ("clk200", 0, Subsignal("p", Pins("J19"), IOStandard("DIFF_SSTL15")), Subsignal("n", Pins("H19"), IOStandard("DIFF_SSTL15")) ), - # leds + # Leds ("user_led", 0, Pins("G3"), IOStandard("LVCMOS33")), ("user_led", 1, Pins("H3"), IOStandard("LVCMOS33")), ("user_led", 2, Pins("G4"), IOStandard("LVCMOS33")), ("user_led", 3, Pins("H4"), IOStandard("LVCMOS33")), - # spiflash + # SPIFlash ("spiflash", 0, Subsignal("cs_n", Pins("T19")), Subsignal("mosi", Pins("P22")), @@ -36,7 +36,7 @@ _io = [ IOStandard("LVCMOS33") ), - # pcie + # PCIe ("pcie_clkreq_n", 0, Pins("G1"), IOStandard("LVCMOS33")), ("pcie_x4", 0, Subsignal("rst_n", Pins("J1"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")), @@ -48,7 +48,7 @@ _io = [ Subsignal("tx_n", Pins("A6 A4 C5 C7")), ), - # dram + # DDR3 SDRAM ("ddram", 0, Subsignal("a", Pins( "M15 L21 M16 L18 K21 M18 M21 N20", diff --git a/litex_boards/platforms/aller.py b/litex_boards/platforms/aller.py index f70dbab..e247084 100644 --- a/litex_boards/platforms/aller.py +++ b/litex_boards/platforms/aller.py @@ -12,15 +12,15 @@ from litex.build.openocd import OpenOCD # IOs ---------------------------------------------------------------------------------------------- _io = [ - # clk / rst + # Clk / Rst ("clk100", 0, Pins("W19"), IOStandard("LVCMOS33")), - # leds (only a single rgb led, aliased here also) + # Leds (only a single rgb led, aliased here also) ("user_led", 0, Pins("AB21"), IOStandard("LVCMOS33")), ("user_led", 1, Pins("AB22"), IOStandard("LVCMOS33")), ("user_led", 2, Pins("U20"), IOStandard("LVCMOS33")), - # rgb led, active-low + # RGB led, active-low ("rgb_led", 0, Subsignal("r", Pins("AB21")), Subsignal("g", Pins("AB22")), @@ -28,7 +28,7 @@ _io = [ IOStandard("LVCMOS33"), ), - # flash + # SPIFlash ("flash", 0, Subsignal("cs_n", Pins("T19")), Subsignal("mosi", Pins("P22")), @@ -37,14 +37,13 @@ _io = [ Subsignal("rst_n", Pins("R19")), IOStandard("LVCMOS33") ), - ("flash4x", 0, # clock needs to be accessed through STARTUPE2 Subsignal("cs_n", Pins("T19")), Subsignal("dq", Pins("P22", "R22", "P21", "R21")), IOStandard("LVCMOS33") ), - # tpm + # TPM ("tpm", 0, Subsignal("clk", Pins("W20")), Subsignal("rst_n", Pins("V19")), @@ -54,7 +53,7 @@ _io = [ IOStandard("LVCMOS33"), ), - # pcie + # PCIe ("pcie_x1", 0, Subsignal("rst_n", Pins("AB20"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")), Subsignal("clk_p", Pins("F6")), @@ -75,7 +74,7 @@ _io = [ Subsignal("tx_n", Pins("A4 C5 A6 C7")) ), - # dram + # DDR3 SDRAM ("ddram", 0, Subsignal("a", Pins( "U6 T5 Y6 T6 V2 T4 Y2 R2", diff --git a/litex_boards/platforms/alveo_u250.py b/litex_boards/platforms/alveo_u250.py index 83f5680..3cfe6a8 100644 --- a/litex_boards/platforms/alveo_u250.py +++ b/litex_boards/platforms/alveo_u250.py @@ -14,7 +14,7 @@ from litex.build.xilinx import XilinxPlatform, VivadoProgrammer # IOs (initially auto-generated by extract_xdc_pins.py) --------------------------------------------- _io = [ - # clk / rst + # Clk / Rst ("clk300", 0, Subsignal("n", Pins("AY38"), IOStandard("DIFF_SSTL12")), Subsignal("p", Pins("AY37"), IOStandard("DIFF_SSTL12")), @@ -33,24 +33,25 @@ _io = [ ), ("cpu_reset", 0, Pins("AL20"), IOStandard("LVCMOS12")), - # led + # Leds ("user_led", 0, Pins("BC21"), IOStandard("LVCMOS12")), ("user_led", 1, Pins("BB21"), IOStandard("LVCMOS12")), ("user_led", 2, Pins("BA20"), IOStandard("LVCMOS12")), - # switches + # Switches ("set_sw", 0, Pins("AL21")), ("user_sw", 0, Pins("AN22"), IOStandard("LVCMOS12")), ("user_sw", 1, Pins("AM19"), IOStandard("LVCMOS12")), ("user_sw", 2, Pins("AL19"), IOStandard("LVCMOS12")), ("user_sw", 3, Pins("AP20"), IOStandard("LVCMOS12")), - # gpio + # GPIOs ("gpio_msp", 0, Pins("AR20"), IOStandard("LVCMOS12")), ("gpio_msp", 1, Pins("AM20"), IOStandard("LVCMOS12")), ("gpio_msp", 2, Pins("AM21"), IOStandard("LVCMOS12")), ("gpio_msp", 3, Pins("AN21"), IOStandard("LVCMOS12")), + # Serial ("serial", 0, Subsignal("rx", Pins("BF18"), IOStandard("LVCMOS12")), Subsignal("tx", Pins("BB20"), IOStandard("LVCMOS12")), @@ -60,7 +61,7 @@ _io = [ Subsignal("tx", Pins("BB19"), IOStandard("LVCMOS12")), ), - # ddram + # DDR4 SDRAM ("ddram_reset_gate", 0, Pins("AU21"), IOStandard("LVCMOS12")), ("ddram", 0, Subsignal("a", Pins( @@ -235,14 +236,14 @@ _io = [ Misc("SLEW=FAST") ), - # i2c + # I2C ("i2c_rst_n", 0, Pins("BF19"), IOStandard("LVCMOS12")), ("i2c", 0, Subsignal("scl", Pins("BF20"), IOStandard("LVCMOS12")), Subsignal("sda", Pins("BF17"), IOStandard("LVCMOS12")), ), - # si570 + # SI570 Clock ("user_si570_clock", 0, Subsignal("n", Pins("AV19"), IOStandard("DIFF_SSTL12")), Subsignal("p", Pins("AU19"), IOStandard("DIFF_SSTL12")), @@ -256,7 +257,7 @@ _io = [ Subsignal("p", Pins("T11")), ), - # pcie + # PCIe ("pcie_x16", 0, Subsignal("rst_n", Pins("BD21"), IOStandard("LVCMOS12")), Subsignal("clk_n", Pins("AM10")), @@ -275,7 +276,7 @@ _io = [ "AP7 AR9 AT7 AU9 AV7 BB5 BD5 BF5")), ), - # pcie + # PCIe ("pcie_x4", 0, Subsignal("rst_n", Pins("BD21"), IOStandard("LVCMOS12")), Subsignal("clk_n", Pins("AM10")), @@ -286,7 +287,7 @@ _io = [ Subsignal("tx_p", Pins("AF7 AG9 AH7 AJ9")), ), - # qsfp28 + # QSFP28 ("qsfp28", 0, Subsignal("clk_n", Pins("K10")), Subsignal("clk_p", Pins("K11")), @@ -321,6 +322,8 @@ _io = [ ), ] +# Connectors --------------------------------------------------------------------------------------- + _connectors = [] # Platform ----------------------------------------------------------------------------------------- diff --git a/litex_boards/platforms/arty.py b/litex_boards/platforms/arty.py index b0d8381..b6dee75 100644 --- a/litex_boards/platforms/arty.py +++ b/litex_boards/platforms/arty.py @@ -12,6 +12,12 @@ from litex.build.openocd import OpenOCD # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst + ("clk100", 0, Pins("E3"), IOStandard("LVCMOS33")), + ("cpu_reset", 0, Pins("C2"), IOStandard("LVCMOS33")), + + + # Leds ("user_led", 0, Pins("H5"), IOStandard("LVCMOS33")), ("user_led", 1, Pins("J5"), IOStandard("LVCMOS33")), ("user_led", 2, Pins("T9"), IOStandard("LVCMOS33")), @@ -23,21 +29,18 @@ _io = [ Subsignal("b", Pins("E1")), IOStandard("LVCMOS33"), ), - ("rgb_led", 1, Subsignal("r", Pins("G3")), Subsignal("g", Pins("J4")), Subsignal("b", Pins("G4")), IOStandard("LVCMOS33"), ), - ("rgb_led", 2, Subsignal("r", Pins("J3")), Subsignal("g", Pins("J2")), Subsignal("b", Pins("H4")), IOStandard("LVCMOS33"), ), - ("rgb_led", 3, Subsignal("r", Pins("K1")), Subsignal("g", Pins("H6")), @@ -45,26 +48,26 @@ _io = [ IOStandard("LVCMOS33"), ), + # Switches ("user_sw", 0, Pins("A8"), IOStandard("LVCMOS33")), ("user_sw", 1, Pins("C11"), IOStandard("LVCMOS33")), ("user_sw", 2, Pins("C10"), IOStandard("LVCMOS33")), ("user_sw", 3, Pins("A10"), IOStandard("LVCMOS33")), + # Buttons ("user_btn", 0, Pins("D9"), IOStandard("LVCMOS33")), ("user_btn", 1, Pins("C9"), IOStandard("LVCMOS33")), ("user_btn", 2, Pins("B9"), IOStandard("LVCMOS33")), ("user_btn", 3, Pins("B8"), IOStandard("LVCMOS33")), - ("clk100", 0, Pins("E3"), IOStandard("LVCMOS33")), - - ("cpu_reset", 0, Pins("C2"), IOStandard("LVCMOS33")), - + # Serial ("serial", 0, Subsignal("tx", Pins("D10")), Subsignal("rx", Pins("A9")), IOStandard("LVCMOS33") ), + # SPI ("spi", 0, Subsignal("clk", Pins("F1")), Subsignal("cs_n", Pins("C1")), @@ -73,6 +76,7 @@ _io = [ IOStandard("LVCMOS33"), ), + # I2C ("i2c", 0, Subsignal("scl", Pins("L18")), Subsignal("sda", Pins("M18")), @@ -81,12 +85,7 @@ _io = [ IOStandard("LVCMOS33"), ), - ("spiflash4x", 0, - Subsignal("cs_n", Pins("L13")), - Subsignal("clk", Pins("L16")), - Subsignal("dq", Pins("K17", "K18", "L14", "M14")), - IOStandard("LVCMOS33") - ), + # SPIFlash ("spiflash", 0, Subsignal("cs_n", Pins("L13")), Subsignal("clk", Pins("L16")), @@ -96,7 +95,14 @@ _io = [ Subsignal("hold", Pins("M14")), IOStandard("LVCMOS33"), ), + ("spiflash4x", 0, + Subsignal("cs_n", Pins("L13")), + Subsignal("clk", Pins("L16")), + Subsignal("dq", Pins("K17", "K18", "L14", "M14")), + IOStandard("LVCMOS33") + ), + # DDR3 SDRAM ("ddram", 0, Subsignal("a", Pins( "R2 M6 N4 T1 N6 R7 V6 U7", @@ -127,6 +133,7 @@ _io = [ Misc("SLEW=FAST"), ), + # MII Ethernet ("eth_ref_clk", 0, Pins("G18"), IOStandard("LVCMOS33")), ("eth_clocks", 0, Subsignal("tx", Pins("H16")), diff --git a/litex_boards/platforms/arty_s7.py b/litex_boards/platforms/arty_s7.py index c8fbf7b..a2a6724 100644 --- a/litex_boards/platforms/arty_s7.py +++ b/litex_boards/platforms/arty_s7.py @@ -12,6 +12,11 @@ from litex.build.openocd import OpenOCD # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst + ("clk100", 0, Pins("R2"), IOStandard("SSTL135")), + ("cpu_reset", 0, Pins("C18"), IOStandard("LVCMOS33")), + + # Leds ("user_led", 0, Pins("E18"), IOStandard("LVCMOS33")), ("user_led", 1, Pins("F13"), IOStandard("LVCMOS33")), ("user_led", 2, Pins("E13"), IOStandard("LVCMOS33")), @@ -23,7 +28,6 @@ _io = [ Subsignal("b", Pins("F15")), IOStandard("LVCMOS33") ), - ("rgb_led", 1, Subsignal("r", Pins("E15")), Subsignal("g", Pins("F18")), @@ -31,6 +35,7 @@ _io = [ IOStandard("LVCMOS33") ), + # Switches ("user_sw", 0, Pins("H14"), IOStandard("LVCMOS33")), ("user_sw", 1, Pins("H18"), IOStandard("LVCMOS33")), ("user_sw", 2, Pins("G18"), IOStandard("LVCMOS33")), @@ -41,15 +46,14 @@ _io = [ ("user_btn", 2, Pins("J16"), IOStandard("LVCMOS33")), ("user_btn", 3, Pins("H13"), IOStandard("LVCMOS33")), - ("clk100", 0, Pins("R2"), IOStandard("SSTL135")), - - ("cpu_reset", 0, Pins("C18"), IOStandard("LVCMOS33")), - + # Serial ("serial", 0, Subsignal("tx", Pins("R12")), Subsignal("rx", Pins("V12")), - IOStandard("LVCMOS33")), + IOStandard("LVCMOS33") + ), + # SPI ("spi", 0, Subsignal("clk", Pins("G16")), Subsignal("cs_n", Pins("H16")), @@ -58,18 +62,14 @@ _io = [ IOStandard("LVCMOS33") ), + # I2C ("i2c", 0, Subsignal("scl", Pins("J14")), Subsignal("sda", Pins("J13")), IOStandard("LVCMOS33"), ), - ("spiflash4x", 0, # clock needs to be accessed through STARTUPE2 - Subsignal("cs_n", Pins("M13")), - Subsignal("clk", Pins("D11")), - Subsignal("dq", Pins("K17", "K18", "L14", "M15")), - IOStandard("LVCMOS33") - ), + # SPIFlash ("spiflash", 0, # clock needs to be accessed through STARTUPE2 Subsignal("cs_n", Pins("M13")), Subsignal("clk", Pins("D11")), @@ -79,7 +79,14 @@ _io = [ Subsignal("hold", Pins("M15")), IOStandard("LVCMOS33") ), + ("spiflash4x", 0, # clock needs to be accessed through STARTUPE2 + Subsignal("cs_n", Pins("M13")), + Subsignal("clk", Pins("D11")), + Subsignal("dq", Pins("K17", "K18", "L14", "M15")), + IOStandard("LVCMOS33") + ), + # DDR3 SDRAM ("ddram", 0, Subsignal("a", Pins( "U2 R4 V2 V4 T3 R7 V6 T6", diff --git a/litex_boards/platforms/avalanche.py b/litex_boards/platforms/avalanche.py index 775d099..1954511 100644 --- a/litex_boards/platforms/avalanche.py +++ b/litex_boards/platforms/avalanche.py @@ -10,31 +10,29 @@ from litex.build.microsemi import MicrosemiPlatform # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst ("clk50", 0, Pins("R1"), IOStandard("LVCMOS25")), ("clk50", 1, Pins("J3"), IOStandard("LVCMOS25")), - ("rst_n", 0, Pins("F5"), IOStandard("LVCMOS33")), + # Leds ("user_led", 0, Pins("D6"), IOStandard("LVCMOS33")), ("user_led", 1, Pins("D7"), IOStandard("LVCMOS33")), ("user_led", 2, Pins("D8"), IOStandard("LVCMOS33")), ("user_led", 3, Pins("D9"), IOStandard("LVCMOS33")), + # Buttons ("user_btn", 0, Pins("E13"), IOStandard("LVCMOS33")), ("user_btn", 1, Pins("E14"), IOStandard("LVCMOS33")), + # Serial ("serial", 0, Subsignal("tx", Pins("F17")), Subsignal("rx", Pins("F16")), IOStandard("LVCMOS33") ), - ("spiflash4x", 0, - Subsignal("clk", Pins("J1")), - Subsignal("cs_n", Pins("H1")), - Subsignal("dq", Pins("F2 F1 M7 M8")), - IOStandard("LVCMOS25") - ), + # SPIFlash ("spiflash", 0, Subsignal("clk", Pins("J1")), Subsignal("cs_n", Pins("H1")), @@ -44,7 +42,14 @@ _io = [ Subsignal("hold", Pins("M8")), IOStandard("LVCMOS25"), ), + ("spiflash4x", 0, + Subsignal("clk", Pins("J1")), + Subsignal("cs_n", Pins("H1")), + Subsignal("dq", Pins("F2 F1 M7 M8")), + IOStandard("LVCMOS25") + ), + # DDR3 SDRAM ("ddram", 0, Subsignal("a", Pins( "U5 U4 V4 W3 V5 W4 Y3 AA3", @@ -69,6 +74,7 @@ _io = [ Subsignal("reset_n", Pins("AB7"), IOStandard("SSTL15II")), ), + # Ethernet ("eth_clocks", 0, Subsignal("tx", Pins("J8")), Subsignal("rx", Pins("K3")), diff --git a/litex_boards/platforms/c10lprefkit.py b/litex_boards/platforms/c10lprefkit.py index 74a76a8..933382d 100644 --- a/litex_boards/platforms/c10lprefkit.py +++ b/litex_boards/platforms/c10lprefkit.py @@ -12,28 +12,32 @@ from litex.build.altera.programmer import USBBlaster # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst ("clk12", 0, Pins("G21"), IOStandard("3.3-V LVTTL")), ("clk25", 0, Pins("AA12"), IOStandard("3.3-V LVTTL")), + ("cpu_reset", 0, Pins("V15"), IOStandard("3.3-V LVTTL")), + # Leds ("user_led", 0, Pins("C18"), IOStandard("3.3-V LVTTL")), ("user_led", 1, Pins("D19"), IOStandard("3.3-V LVTTL")), ("user_led", 2, Pins("C19"), IOStandard("3.3-V LVTTL")), ("user_led", 3, Pins("C17"), IOStandard("3.3-V LVTTL")), ("user_led", 4, Pins("D18"), IOStandard("3.3-V LVTTL")), - ("cpu_reset", 0, Pins("V15"), IOStandard("3.3-V LVTTL")), - + # Switches ("sw", 0, Pins("U10"), IOStandard("3.3-V LVTTL")), ("sw", 1, Pins("U11"), IOStandard("3.3-V LVTTL")), ("sw", 2, Pins("V11"), IOStandard("3.3-V LVTTL")), ("sw", 3, Pins("T10"), IOStandard("3.3-V LVTTL")), ("sw", 4, Pins("T11"), IOStandard("3.3-V LVTTL")), + # Serial ("serial", 0, Subsignal("tx", Pins("B21"), IOStandard("3.3-V LVTTL")), Subsignal("rx", Pins("C20"), IOStandard("3.3-V LVTTL")), ), + # SDR SDRAM ("sdram_clock", 0, Pins("AA3"), IOStandard("3.3-V LVTTL")), ("sdram", 0, Subsignal("a", Pins( @@ -52,14 +56,16 @@ _io = [ IOStandard("3.3-V LVTTL") ), + # ECPS ("epcs", 0, Subsignal("data0", Pins("K1")), - Subsignal("dclk", Pins("K2")), - Subsignal("ncs0", Pins("E2")), - Subsignal("asd0", Pins("D1")), + Subsignal("dclk", Pins("K2")), + Subsignal("ncs0", Pins("E2")), + Subsignal("asd0", Pins("D1")), IOStandard("3.3-V LVTTL") ), + # HyperRAM ("hyperram", 0, Subsignal("clk", Pins("T16")), Subsignal("rst_n", Pins("U12")), @@ -69,11 +75,13 @@ _io = [ IOStandard("3.3-V LVTTL") ), + # GPIO Leds ("gpio_leds", 0, Pins("AB10 AA10 AA9 Y10 W10 U9 U8 U7"), IOStandard("3.3-V LVTTL") ), + # MII Ethernet ("eth_clocks", 0, Subsignal("tx", Pins("U21")), Subsignal("rx", Pins("V22")), @@ -92,7 +100,6 @@ _io = [ Subsignal("crs", Pins("R20")), IOStandard("3.3-V LVTTL"), ), - ("eth_clocks", 1, Subsignal("tx", Pins("N16")), Subsignal("rx", Pins("V22")), diff --git a/litex_boards/platforms/camlink_4k.py b/litex_boards/platforms/camlink_4k.py index eaa5449..39ba685 100644 --- a/litex_boards/platforms/camlink_4k.py +++ b/litex_boards/platforms/camlink_4k.py @@ -16,17 +16,21 @@ from litex.build.lattice import LatticePlatform # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst ("clk27", 0, Pins("B11"), IOStandard("LVCMOS25")), + # Leds ("user_led", 0, Pins("A6"), IOStandard("LVCMOS25")), ("user_led", 1, Pins("A9"), IOStandard("LVCMOS25")), + # Serial ("serial", 0, Subsignal("tx", Pins("A6")), # led0 Subsignal("rx", Pins("A9")), # led1 IOStandard("LVCMOS25") ), + # DDR3 SDRAM ("ddram", 0, Subsignal("a", Pins( "P2 L2 N1 P1 N5 M1 M3 N4", diff --git a/litex_boards/platforms/colorlight_5a_75b.py b/litex_boards/platforms/colorlight_5a_75b.py index db4fd62..13f2353 100644 --- a/litex_boards/platforms/colorlight_5a_75b.py +++ b/litex_boards/platforms/colorlight_5a_75b.py @@ -14,16 +14,16 @@ from litex.build.lattice.programmer import OpenOCDJTAGProgrammer # IOs ---------------------------------------------------------------------------------------------- _io_v6_1 = [ # Documented by @smunaut - # clock + # Clk ("clk25", 0, Pins("P3"), IOStandard("LVCMOS33")), - # led + # Led ("user_led_n", 0, Pins("U16"), IOStandard("LVCMOS33")), - # btn + # Button ("user_btn_n", 0, Pins("R16"), IOStandard("LVCMOS33")), - # serial + # Serial # There seems to be some capacitance on KEY+ pin, so high baudrates may not work (>9600bps). ("serial", 0, Subsignal("tx", Pins("U16")), # led (J19 DATA_LED-) @@ -31,7 +31,7 @@ _io_v6_1 = [ # Documented by @smunaut IOStandard("LVCMOS33") ), - # spi flash (GD25Q16CSIG) + # SPIFlash (GD25Q16CSIG) ("spiflash", 0, Subsignal("cs_n", Pins("R2")), Subsignal("clk", Pins("U3")), @@ -40,7 +40,7 @@ _io_v6_1 = [ # Documented by @smunaut IOStandard("LVCMOS33"), ), - # sdram (EM636165-6G) + # SDRAM SDRAM (EM636165-6G) ("sdram_clock", 0, Pins("B9"), IOStandard("LVCMOS33")), ("sdram", 0, Subsignal("a", Pins( @@ -62,7 +62,7 @@ _io_v6_1 = [ # Documented by @smunaut Misc("SLEWRATE=FAST") ), - # ethernet (B50612D) + # RGMII Ethernet (B50612D) ("eth_clocks", 0, Subsignal("tx", Pins("G1")), Subsignal("rx", Pins("H2")), @@ -78,7 +78,6 @@ _io_v6_1 = [ # Documented by @smunaut Subsignal("tx_data", Pins("G2 H1 J1 J3")), IOStandard("LVCMOS33") ), - ("eth_clocks", 1, Subsignal("tx", Pins("U19")), Subsignal("rx", Pins("L19")), @@ -97,23 +96,23 @@ _io_v6_1 = [ # Documented by @smunaut ] _io_v7_0 = [ # Documented by @miek - # clock + # Clk ("clk25", 0, Pins("P6"), IOStandard("LVCMOS33")), - # led + # Led ("user_led_n", 0, Pins("P11"), IOStandard("LVCMOS33")), - # btn + # Button ("user_btn_n", 0, Pins("M13"), IOStandard("LVCMOS33")), - # serial + # Serial ("serial", 0, Subsignal("tx", Pins("P11")), # led (J19 DATA_LED-) Subsignal("rx", Pins("M13")), # btn (J19 KEY+) IOStandard("LVCMOS33") ), - # spiflash (W25Q32JV) + # SPIFlash (W25Q32JV) ("spiflash", 0, # clk Subsignal("cs_n", Pins("N8")), @@ -123,7 +122,7 @@ _io_v7_0 = [ # Documented by @miek IOStandard("LVCMOS33"), ), - # sdram (M12616161A) + # SDR SDRAM (M12616161A) ("sdram_clock", 0, Pins("C6"), IOStandard("LVCMOS33")), ("sdram", 0, Subsignal("a", Pins( @@ -145,7 +144,7 @@ _io_v7_0 = [ # Documented by @miek Misc("SLEWRATE=FAST") ), - # ethernet (B50612D) + # RGMII Ethernet (B50612D) ("eth_clocks", 0, Subsignal("tx", Pins("M2")), Subsignal("rx", Pins("M1")), @@ -177,6 +176,7 @@ _io_v7_0 = [ # Documented by @miek IOStandard("LVCMOS33") ), + # USB ("usb", 0, Subsignal("d_p", Pins("M8")), Subsignal("d_n", Pins("R2")), @@ -185,7 +185,7 @@ _io_v7_0 = [ # Documented by @miek ), ] -# from https://github.com/miek/chubby75/blob/5a-75b-v7_pinout/5a-75b/hardware_V6.1.md +# From https://github.com/miek/chubby75/blob/5a-75b-v7_pinout/5a-75b/hardware_V6.1.md _connectors_v6_1 = [ ("j1", "B3 A2 B2 - B1 C2 C1 J17 F1 E2 E1 F2 C18 J18 H16 -"), ("j2", "D2 H3 H4 - J4 B4 A3 J17 F1 E2 E1 F2 C18 J18 H16 -"), @@ -197,7 +197,7 @@ _connectors_v6_1 = [ ("j8", "B20 C20 B19 - B18 A19 A18 J17 F1 E2 E1 F2 C18 J18 H16 -"), ] -# from https://github.com/q3k/chubby75/blob/master/5a-75b/hardware_V7.0.md +# From https://github.com/q3k/chubby75/blob/master/5a-75b/hardware_V7.0.md _connectors_v7_0 = [ ("j1", "F3 F1 G3 - G2 H3 H5 F15 L2 K1 J5 K2 B16 J14 F12 -"), ("j2", "J4 K3 G1 - K4 C2 E3 F15 L2 K1 J5 K2 B16 J14 F12 -"), @@ -209,8 +209,6 @@ _connectors_v7_0 = [ ("j8", "A15 F16 A14 - E13 B14 A13 F15 L2 K1 J5 K2 B16 J14 F12 -"), ] - - # Platform ----------------------------------------------------------------------------------------- class Platform(LatticePlatform): diff --git a/litex_boards/platforms/colorlight_5a_75e.py b/litex_boards/platforms/colorlight_5a_75e.py index 96b8f87..0e2b88c 100644 --- a/litex_boards/platforms/colorlight_5a_75e.py +++ b/litex_boards/platforms/colorlight_5a_75e.py @@ -16,25 +16,24 @@ from litex.build.lattice.programmer import OpenOCDJTAGProgrammer # Documented by @derekmulcahy _io_v7_1 = [ - # clock + # Clk ("clk25", 0, Pins("P6"), IOStandard("LVCMOS33")), - # led + # Led ("user_led_n", 0, Pins("P11"), IOStandard("LVCMOS33")), - # btn + # Button ("user_btn_n", 0, Pins("M13"), IOStandard("LVCMOS33")), - # serial + # Serial ("serial", 0, Subsignal("tx", Pins("P11")), # led (J19 DATA_LED-) Subsignal("rx", Pins("M13")), # btn (J19 KEY+) IOStandard("LVCMOS33") ), - # spiflash (W25Q32JV) + # SPIFlash (W25Q32JV) ("spiflash", 0, - # clk Subsignal("cs_n", Pins("N8")), #Subsignal("clk", Pins("")), driven through USRMCLK Subsignal("mosi", Pins("T8")), @@ -42,7 +41,7 @@ _io_v7_1 = [ IOStandard("LVCMOS33"), ), - # sdram (M12616161A) + # SDR SDRAM (M12616161A) ("sdram_clock", 0, Pins("C6"), IOStandard("LVCMOS33")), ("sdram", 0, Subsignal("a", Pins( @@ -64,7 +63,7 @@ _io_v7_1 = [ Misc("SLEWRATE=FAST") ), - # ethernet (B50612D) + # RGMII Ethernet (B50612D) ("eth_clocks", 0, Subsignal("tx", Pins("M2")), Subsignal("rx", Pins("M1")), @@ -99,25 +98,24 @@ _io_v7_1 = [ # Documented by @adamgreig _io_v6_0 = [ - # clock + # Clk ("clk25", 0, Pins("P6"), IOStandard("LVCMOS33")), - # led + # Led ("user_led_n", 0, Pins("T6"), IOStandard("LVCMOS33")), - # btn + # Button ("user_btn_n", 0, Pins("R7"), IOStandard("LVCMOS33")), - # serial + # Serial ("serial", 0, Subsignal("tx", Pins("T6")), # led (J19 DATA_LED-) Subsignal("rx", Pins("R7")), # btn (J19 KEY+) IOStandard("LVCMOS33") ), - # spiflash (25Q32JVSIQ) + # SPIFlash (25Q32JVSIQ) ("spiflash", 0, - # clk Subsignal("cs_n", Pins("N8")), #Subsignal("clk", Pins("")), driven through USRMCLK Subsignal("mosi", Pins("T8")), @@ -125,7 +123,7 @@ _io_v6_0 = [ IOStandard("LVCMOS33"), ), - # sdram (M12L64322A-5T) + # SDR SDRAM (M12L64322A-5T) ("sdram_clock", 0, Pins("C8"), IOStandard("LVCMOS33")), ("sdram", 0, Subsignal("a", Pins("A9 B9 B10 C10 D9 C9 E9 D8 E8 C7 B8")), @@ -145,7 +143,7 @@ _io_v6_0 = [ IOStandard("LVCMOS33"), ), - # ethernet (RTL8211FD) + # RGMII Ethernet (RTL8211FD) ("eth_clocks", 0, Subsignal("tx", Pins("L1")), Subsignal("rx", Pins("J1")), @@ -178,7 +176,7 @@ _io_v6_0 = [ ), ] -# from https://github.com/q3k/chubby75/blob/master/5a-75e/hardware_V7.1.md +# From https://github.com/q3k/chubby75/blob/master/5a-75e/hardware_V7.1.md _connectors_v7_1 = [ ("j1", "F3 F1 G3 - G2 H3 H5 F15 L2 K1 J5 K2 B16 J14 F12 -"), ("j2", "G4 G5 J2 - H2 J1 J3 F15 L2 K1 J5 K2 B16 J14 F12 -"), @@ -198,7 +196,7 @@ _connectors_v7_1 = [ ("j16", "G13 G12 E15 - F14 F13 C13 F15 L2 K1 J5 K2 B16 J14 F12 -"), ] -# from https://github.com/q3k/chubby75/blob/master/5a-75e/hardware_V6.0.md +# From https://github.com/q3k/chubby75/blob/master/5a-75e/hardware_V6.0.md _connectors_v6_0 = [ ("j1", "C4 D4 E4 - D3 E3 F4 N4 N5 N3 P3 P4 M3 N1 M4 -"), ("j2", "F3 F5 G3 - G4 H3 H4 N4 N5 N3 P3 P4 M3 N1 M4 -"), @@ -218,7 +216,6 @@ _connectors_v6_0 = [ ("j16", "F14 G13 F12 - F13 F14 E14 N4 N5 N3 P3 P4 M3 N1 M4 -"), ] - # Platform ----------------------------------------------------------------------------------------- class Platform(LatticePlatform): diff --git a/litex_boards/platforms/de0nano.py b/litex_boards/platforms/de0nano.py index 7e6196c..4470052 100644 --- a/litex_boards/platforms/de0nano.py +++ b/litex_boards/platforms/de0nano.py @@ -11,8 +11,10 @@ from litex.build.altera.programmer import USBBlaster # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk ("clk50", 0, Pins("R8"), IOStandard("3.3-V LVTTL")), + # Leds ("user_led", 0, Pins("A15"), IOStandard("3.3-V LVTTL")), ("user_led", 1, Pins("A13"), IOStandard("3.3-V LVTTL")), ("user_led", 2, Pins("B13"), IOStandard("3.3-V LVTTL")), @@ -22,14 +24,17 @@ _io = [ ("user_led", 6, Pins("B1"), IOStandard("3.3-V LVTTL")), ("user_led", 7, Pins("L3"), IOStandard("3.3-V LVTTL")), + # Button ("key", 0, Pins("J15"), IOStandard("3.3-V LVTTL")), ("key", 1, Pins("E1"), IOStandard("3.3-V LVTTL")), + # Switches ("sw", 0, Pins("M1"), IOStandard("3.3-V LVTTL")), ("sw", 1, Pins("T8"), IOStandard("3.3-V LVTTL")), ("sw", 2, Pins("B9"), IOStandard("3.3-V LVTTL")), ("sw", 3, Pins("M15"), IOStandard("3.3-V LVTTL")), + # Serial ("serial", 0, # Compatible with cheap FT232 based cables (ex: Gaoominy 6Pin Ftdi Ft232Rl Ft232) # GND on JP1 Pin 12. @@ -37,6 +42,7 @@ _io = [ Subsignal("rx", Pins("B4"), IOStandard("3.3-V LVTTL")) # GPIO_05 (JP1 Pin 8) ), + # SDR SDRAM ("sdram_clock", 0, Pins("R4"), IOStandard("3.3-V LVTTL")), ("sdram", 0, Subsignal("a", Pins( @@ -55,6 +61,7 @@ _io = [ IOStandard("3.3-V LVTTL") ), + # ECPS ("epcs", 0, Subsignal("data0", Pins("H2")), Subsignal("dclk", Pins("H1")), @@ -63,18 +70,21 @@ _io = [ IOStandard("3.3-V LVTTL") ), + # I2C ("i2c", 0, Subsignal("sclk", Pins("F2")), Subsignal("sdat", Pins("F1")), IOStandard("3.3-V LVTTL") ), - ("g_sensor", 0, + # Accelerometer + ("acc", 0, Subsignal("cs_n", Pins("G5")), Subsignal("int", Pins("M2")), IOStandard("3.3-V LVTTL") ), + # ADC ("adc", 0, Subsignal("cs_n", Pins("A10")), Subsignal("saddr", Pins("B10")), @@ -83,6 +93,7 @@ _io = [ IOStandard("3.3-V LVTTL") ), + # GPIOs ("gpio_0", 0, Pins( "D3 C3 A2 A3 B3 B4 A4 B5", "A5 D5 B6 A6 B7 D6 A7 C6", diff --git a/litex_boards/platforms/de10lite.py b/litex_boards/platforms/de10lite.py index 20537ac..628e691 100644 --- a/litex_boards/platforms/de10lite.py +++ b/litex_boards/platforms/de10lite.py @@ -11,15 +11,12 @@ from litex.build.altera.programmer import USBBlaster # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst ("clk10", 0, Pins("N5"), IOStandard("3.3-V LVTTL")), ("clk50", 0, Pins("P11"), IOStandard("3.3-V LVTTL")), ("clk50", 1, Pins("N14"), IOStandard("3.3-V LVTTL")), - ("serial", 0, - Subsignal("tx", Pins("V10"), IOStandard("3.3-V LVTTL")), # JP1 GPIO[0] - Subsignal("rx", Pins("W10"), IOStandard("3.3-V LVTTL")) # JP1 GPIO[1] - ), - + # Leds ("user_led", 0, Pins("A8"), IOStandard("3.3-V LVTTL")), ("user_led", 1, Pins("A9"), IOStandard("3.3-V LVTTL")), ("user_led", 2, Pins("A10"), IOStandard("3.3-V LVTTL")), @@ -31,9 +28,11 @@ _io = [ ("user_led", 8, Pins("A11"), IOStandard("3.3-V LVTTL")), ("user_led", 9, Pins("B11"), IOStandard("3.3-V LVTTL")), + # Buttons ("user_btn", 0, Pins("B8"), IOStandard("3.3-V LVTTL")), ("user_btn", 1, Pins("A7"), IOStandard("3.3-V LVTTL")), + # Switches ("user_sw", 0, Pins("C10"), IOStandard("3.3-V LVTTL")), ("user_sw", 1, Pins("C11"), IOStandard("3.3-V LVTTL")), ("user_sw", 2, Pins("D12"), IOStandard("3.3-V LVTTL")), @@ -45,7 +44,7 @@ _io = [ ("user_sw", 8, Pins("B14"), IOStandard("3.3-V LVTTL")), ("user_sw", 9, Pins("F15"), IOStandard("3.3-V LVTTL")), - # 7-segment displays + # Seven Segment ("seven_seg", 0, Pins("C14 E15 C15 C16 E16 D17 C17 D15"), IOStandard("3.3-V LVTTL")), ("seven_seg", 1, Pins("C18 D18 E18 B16 A17 A18 B17 A16"), IOStandard("3.3-V LVTTL")), ("seven_seg", 2, Pins("B20 A20 B19 A21 B21 C22 B22 A19"), IOStandard("3.3-V LVTTL")), @@ -53,31 +52,13 @@ _io = [ ("seven_seg", 4, Pins("F18 E20 E19 J18 H19 F19 F20 F17"), IOStandard("3.3-V LVTTL")), ("seven_seg", 5, Pins("J20 K20 L18 N18 M20 N19 N20 L19"), IOStandard("3.3-V LVTTL")), - - ("gpio_0", 0, Pins( - "V9 W9 V8 W8 V7 W7 W6 V5", - "W5 AA15 AA14 W13 W12 AB13 AB12 Y11", - "AB11 W11 AB10 AA10 AA9 Y8 AA8 Y7", - "AA7 Y6 AA6 Y5 AA5 Y4 AB3 Y3", - "AB2 AA2"), - IOStandard("3.3-V LVTTL") - ), - ("gpio_1", 0, Pins( - "AB5 AB6 AB7 AB8 AB9 Y10 AA11 AA12", - "AB17 AA17 AB19 AA19 Y19 AB20 AB21 AA20", - "F16"), - IOStandard("3.3-V LVTTL") - ), - - ("vga", 0, - Subsignal("hsync_n", Pins("N3")), - Subsignal("vsync_n", Pins("N1")), - Subsignal("r", Pins("AA1 V1 Y2 Y1")), - Subsignal("g", Pins("W1 T2 R2 R1")), - Subsignal("b", Pins("P1 T1 P4 N2")), - IOStandard("3.3-V LVTTL") + # Serial + ("serial", 0, + Subsignal("tx", Pins("V10"), IOStandard("3.3-V LVTTL")), # JP1 GPIO[0] + Subsignal("rx", Pins("W10"), IOStandard("3.3-V LVTTL")) # JP1 GPIO[1] ), + # SDR SDRAM ("sdram_clock", 0, Pins("L14"), IOStandard("3.3-V LVTTL")), ("sdram", 0, Subsignal("a", Pins( @@ -96,7 +77,18 @@ _io = [ IOStandard("3.3-V LVTTL") ), - ("accelerometer", 0, + # VGA + ("vga", 0, + Subsignal("hsync_n", Pins("N3")), + Subsignal("vsync_n", Pins("N1")), + Subsignal("r", Pins("AA1 V1 Y2 Y1")), + Subsignal("g", Pins("W1 T2 R2 R1")), + Subsignal("b", Pins("P1 T1 P4 N2")), + IOStandard("3.3-V LVTTL") + ), + + # Accelerometer + ("acc", 0, Subsignal("int1", Pins("Y14")), Subsignal("int1", Pins("Y13")), Subsignal("mosi", Pins("V11")), @@ -104,7 +96,23 @@ _io = [ Subsignal("clk", Pins("AB15")), Subsignal("cs_n", Pins("AB16")), IOStandard("3.3-V LVTTL") - ) + ), + + # GPIOs + ("gpio_0", 0, Pins( + "V9 W9 V8 W8 V7 W7 W6 V5", + "W5 AA15 AA14 W13 W12 AB13 AB12 Y11", + "AB11 W11 AB10 AA10 AA9 Y8 AA8 Y7", + "AA7 Y6 AA6 Y5 AA5 Y4 AB3 Y3", + "AB2 AA2"), + IOStandard("3.3-V LVTTL") + ), + ("gpio_1", 0, Pins( + "AB5 AB6 AB7 AB8 AB9 Y10 AA11 AA12", + "AB17 AA17 AB19 AA19 Y19 AB20 AB21 AA20", + "F16"), + IOStandard("3.3-V LVTTL") + ), ] # Platform ----------------------------------------------------------------------------------------- diff --git a/litex_boards/platforms/de10nano.py b/litex_boards/platforms/de10nano.py index e38e0e3..1d524c5 100644 --- a/litex_boards/platforms/de10nano.py +++ b/litex_boards/platforms/de10nano.py @@ -11,10 +11,12 @@ from litex.build.altera.programmer import USBBlaster # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst ("clk50", 0, Pins("V11"), IOStandard("3.3-V LVTTL")), ("clk50", 1, Pins("Y13"), IOStandard("3.3-V LVTTL")), ("clk50", 2, Pins("E11"), IOStandard("3.3-V LVTTL")), + # Leds ("user_led", 0, Pins("W15"), IOStandard("3.3-V LVTTL")), ("user_led", 1, Pins("AA24"), IOStandard("3.3-V LVTTL")), ("user_led", 2, Pins("V16"), IOStandard("3.3-V LVTTL")), @@ -24,31 +26,37 @@ _io = [ ("user_led", 6, Pins("Y16"), IOStandard("3.3-V LVTTL")), ("user_led", 7, Pins("AA23"), IOStandard("3.3-V LVTTL")), + # Buttons ("key", 0, Pins("AH17"), IOStandard("3.3-V LVTTL")), ("key", 1, Pins("AH16"), IOStandard("3.3-V LVTTL")), + # Switches ("user_sw", 0, Pins("Y24"), IOStandard("3.3-V LVTTL")), ("user_sw", 1, Pins("W24"), IOStandard("3.3-V LVTTL")), ("user_sw", 2, Pins("W21"), IOStandard("3.3-V LVTTL")), ("user_sw", 3, Pins("W20"), IOStandard("3.3-V LVTTL")), + # Serial ("serial", 0, Subsignal("tx", Pins("AH9"), IOStandard("3.3-V LVTTL")), # User I/O port on Mister Subsignal("rx", Pins("AG11"), IOStandard("3.3-V LVTTL")) # User I/O port on Mister ), + # Serial ("serial", 1, Subsignal("tx", Pins("AF13"), IOStandard("3.3-V LVTTL")), # Arduino_IO1 Subsignal("rx", Pins("AG13"), IOStandard("3.3-V LVTTL")) # Arduino_IO0 ), - ("g_sensor", 0, + # Accelerometer + ("acc", 0, Subsignal("int", Pins("A17")), Subsignal("sclk", Pins("C18")), Subsignal("sdat", Pins("A19")), IOStandard("3.3-V LVTTL") ), + # ADC ("adc", 0, Subsignal("convst", Pins("U9")), Subsignal("sclk", Pins("V10")), @@ -57,6 +65,7 @@ _io = [ IOStandard("3.3-V LVTTL") ), + # HDMI ("hdmi", 0, Subsignal("tx_d_r", Pins("AS12 AE12 W8 Y8 AD11 AD10 AE11 Y5")), Subsignal("tx_d_g", Pins("AF10 Y4 AE9 AB4 AE7 AF6 AF8 AF5")), @@ -70,12 +79,14 @@ _io = [ IOStandard("3.3-V LVTTL") ), + # I2C ("i2c", 0, Subsignal("scl", Pins("U10")), Subsignal("sda", Pins("AA4")), IOStandard("3.3-V LVTTL") ), + # I2S ("i2s", 0, Subsignal("i2s", Pins("T13")), Subsignal("mclk", Pins("U11")), @@ -85,7 +96,10 @@ _io = [ ), ] +# MiSTer extension board (https://github.com/MiSTer-devel/Main_MiSTer/wiki) ------------------------ + _mister_sdram_module_io = [ + # SDR SDRAM ("sdram_clock", 0, Pins("AD20"), IOStandard("3.3-V LVTTL")), ("sdram", 0, Subsignal("cke", Pins("AG10")), @@ -108,6 +122,7 @@ _mister_sdram_module_io = [ IOStandard("3.3-V LVTTL"), ), + # SDCard ("spisdcard", 0, Subsignal("clk", Pins("AH26")), Subsignal("cs_n", Pins("AF28")), @@ -125,6 +140,7 @@ _mister_sdram_module_io = [ IOStandard("3.3-V LVTTL"), ), + # Outputs ("mister_outputs", 0, Subsignal("led_user", Pins("Y15")), Subsignal("led_hdd", Pins("AA15")), @@ -132,6 +148,7 @@ _mister_sdram_module_io = [ IOStandard("3.3-V LVTTL") ), + # VGA ("vga", 0, Subsignal("red", Pins("AE17 AE20 AF20 AH18 AH19 AF21")), Subsignal("green", Pins("AE19 AG15 AF18 AG18 AG19 AG20")), diff --git a/litex_boards/platforms/de1soc.py b/litex_boards/platforms/de1soc.py index f73ccc0..440d024 100644 --- a/litex_boards/platforms/de1soc.py +++ b/litex_boards/platforms/de1soc.py @@ -11,13 +11,16 @@ from litex.build.altera.programmer import USBBlaster # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk ("clk50", 0, Pins("AF14"), IOStandard("3.3-V LVTTL")), + # Serial ("serial", 0, Subsignal("tx", Pins("AC18"), IOStandard("3.3-V LVTTL")), # JP1 GPIO[0] Subsignal("rx", Pins("Y17"), IOStandard("3.3-V LVTTL")) # JP1 GPIO[1] ), + # SDR SDRAM ("sdram_clock", 0, Pins("AH12"), IOStandard("3.3-V LVTTL")), ("sdram", 0, Subsignal("a", Pins( diff --git a/litex_boards/platforms/de2_115.py b/litex_boards/platforms/de2_115.py index fbac8a9..acb205d 100644 --- a/litex_boards/platforms/de2_115.py +++ b/litex_boards/platforms/de2_115.py @@ -11,13 +11,16 @@ from litex.build.altera.programmer import USBBlaster # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk ("clk50", 0, Pins("Y2"), IOStandard("3.3-V LVTTL")), + # Serial ("serial", 0, Subsignal("tx", Pins("AB22"), IOStandard("3.3-V LVTTL")), # JP5 GPIO[0] Subsignal("rx", Pins("AC15"), IOStandard("3.3-V LVTTL")) # JP5 GPIO[1] ), + # SDR SDRAM ("sdram_clock", 0, Pins("AE5"), IOStandard("3.3-V LVTTL")), ("sdram", 0, Subsignal("a", Pins( diff --git a/litex_boards/platforms/ecp5_evn.py b/litex_boards/platforms/ecp5_evn.py index 15c08b5..8e424e3 100644 --- a/litex_boards/platforms/ecp5_evn.py +++ b/litex_boards/platforms/ecp5_evn.py @@ -13,9 +13,18 @@ import os # IOs ---------------------------------------------------------------------------------------------- _io = [ - ("clk12", 0, Pins("A10"), IOStandard("LVCMOS33")), - ("rst_n", 0, Pins("G2"), IOStandard("LVCMOS33")), + # Clk / Rst + ("clk12", 0, Pins("A10"), IOStandard("LVCMOS33")), + ("clk200", 0, + Subsignal("p", Pins("Y19")), + Subsignal("n", Pins("W20")), + IOStandard("LVDS") + ), + ("ext_clk50", 0, Pins("B11"), IOStandard("LVCMOS33")), + ("ext_clk50_en", 0, Pins("C11"), IOStandard("LVCMOS33")), + ("rst_n", 0, Pins("G2"), IOStandard("LVCMOS33")), + # Leds ("user_led", 0, Pins("A13"), IOStandard("LVCMOS25")), ("user_led", 1, Pins("A12"), IOStandard("LVCMOS25")), ("user_led", 2, Pins("B19"), IOStandard("LVCMOS25")), @@ -25,6 +34,7 @@ _io = [ ("user_led", 6, Pins("A17"), IOStandard("LVCMOS25")), ("user_led", 7, Pins("B17"), IOStandard("LVCMOS25")), + # Buttons ("user_dip_btn", 1, Pins("J1"), IOStandard("LVCMOS33")), ("user_dip_btn", 2, Pins("H1"), IOStandard("LVCMOS33")), ("user_dip_btn", 3, Pins("K1"), IOStandard("LVCMOS33")), @@ -36,31 +46,24 @@ _io = [ ("button_1", 0, Pins("P4"), IOStandard("LVCMOS25")), + # Serial ("serial", 0, Subsignal("rx", Pins("P2"), IOStandard("LVCMOS33")), Subsignal("tx", Pins("P3"), IOStandard("LVCMOS33")), ), - ("spiflashx", 0, + # SPIFlash + ("spiflash", 0, Subsignal("cs_n", Pins("R2"), IOStandard("LVCMOS33")), Subsignal("mosi", Pins("W2"), IOStandard("LVCMOS33")), Subsignal("miso", Pins("V2"), IOStandard("LVCMOS33")), Subsignal("wp", Pins("Y2"), IOStandard("LVCMOS33")), Subsignal("hold", Pins("W1"), IOStandard("LVCMOS33")), ), - ("spiflash4x", 0, Subsignal("cs_n", Pins("R2"), IOStandard("LVCMOS33")), Subsignal("dq", Pins("W2 V2 Y2 W1"), IOStandard("LVCMOS33")), ), - - ("clk200", 0, - Subsignal("p", Pins("Y19")), - Subsignal("n", Pins("W20")), - IOStandard("LVDS") - ), - ("ext_clk50", 0, Pins("B11"), IOStandard("LVCMOS33")), - ("ext_clk50_en", 0, Pins("C11"), IOStandard("LVCMOS33")), ] # Connectors --------------------------------------------------------------------------------------- diff --git a/litex_boards/platforms/ecpix5.py b/litex_boards/platforms/ecpix5.py index 2d11d49..c1fd699 100644 --- a/litex_boards/platforms/ecpix5.py +++ b/litex_boards/platforms/ecpix5.py @@ -11,11 +11,11 @@ from litex.build.lattice.programmer import OpenOCDJTAGProgrammer # IOs ---------------------------------------------------------------------------------------------- _io = [ - # clock / reset + # Clk / Rst ("clk100", 0, Pins("K23"), IOStandard("LVCMOS33")), ("rst_n", 0, Pins("N5"), IOStandard("LVCMOS33")), - # led + # Leds ("rgb_led", 0, Subsignal("r", Pins("U21")), Subsignal("g", Pins("W21")), @@ -41,13 +41,13 @@ _io = [ IOStandard("LVCMOS33"), ), - # serial + # Serial ("serial", 0, Subsignal("rx", Pins("R26"), IOStandard("LVCMOS33")), Subsignal("tx", Pins("R24"), IOStandard("LVCMOS33")), ), - # ddram + # DDR3 SDRAM ("ddram", 0, Subsignal("a", Pins( "T5 M3 L3 V6 K2 W6 K3 L1", @@ -72,7 +72,7 @@ _io = [ Misc("SLEWRATE=FAST"), ), - # ethernet + # RGMII Ethernetx ("eth_clocks", 0, Subsignal("tx", Pins("A12")), Subsignal("rx", Pins("E11")), @@ -89,7 +89,7 @@ _io = [ IOStandard("LVCMOS33") ), - # sdcard + # SDCard ("sdcard", 0, Subsignal("data", Pins("N26 N25 N23 N21"), Misc("PULLMODE=UP")), Subsignal("cmd", Pins("M24"), Misc("PULLMODE=UP")), @@ -101,6 +101,8 @@ _io = [ ), ] +# Connectors --------------------------------------------------------------------------------------- + _connectors = [] # Platform ----------------------------------------------------------------------------------------- diff --git a/litex_boards/platforms/fk33.py b/litex_boards/platforms/fk33.py index 6640ac4..01d3ce2 100644 --- a/litex_boards/platforms/fk33.py +++ b/litex_boards/platforms/fk33.py @@ -13,11 +13,13 @@ from litex.build.xilinx import XilinxPlatform, VivadoProgrammer # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst ("clk200", 0, Subsignal("p", Pins("BC26"), IOStandard("LVDS")), Subsignal("n", Pins("BC27"), IOStandard("LVDS")) ), + # Leds ("user_led", 0, Pins("BD25"), IOStandard("LVCMOS18")), ("user_led", 1, Pins("BE26"), IOStandard("LVCMOS18")), ("user_led", 2, Pins("BD23"), IOStandard("LVCMOS18")), @@ -26,11 +28,13 @@ _io = [ ("user_led", 5, Pins("BB26"), IOStandard("LVCMOS18")), ("user_led", 6, Pins("BB25"), IOStandard("LVCMOS18")), + # I2C ("i2c", Subsignal("scl", Pins("BB24"), IOStandard("LVCMOS18"), Misc("DRIVE=8")), Subsignal("sda", Pins("BA24"), IOStandard("LVCMOS18"), Misc("DRIVE=8")), ), + # PCIe ("pcie_x2", 0, Subsignal("rst_n", Pins("BE24"), IOStandard("LVCMOS18")), Subsignal("clk_p", Pins("AD9")), diff --git a/litex_boards/platforms/fomu_evt.py b/litex_boards/platforms/fomu_evt.py index 2d87246..7c4be02 100644 --- a/litex_boards/platforms/fomu_evt.py +++ b/litex_boards/platforms/fomu_evt.py @@ -16,8 +16,10 @@ from litex.build.lattice.programmer import IceStormProgrammer # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst ("clk48", 0, Pins("44"), IOStandard("LVCMOS33")), + # Leds ("user_led_n", 0, Pins("41"), IOStandard("LVCMOS33")), ("rgb_led", 0, Subsignal("r", Pins("40")), @@ -26,15 +28,18 @@ _io = [ IOStandard("LVCMOS33"), ), + # Buttons ("user_btn_n", 0, Pins("42"), IOStandard("LVCMOS33")), ("user_btn_n", 1, Pins("38"), IOStandard("LVCMOS33")), + # Serial ("serial", 0, Subsignal("rx", Pins("21")), Subsignal("tx", Pins("13"), Misc("PULLUP")), IOStandard("LVCMOS33") ), + # USB ("usb", 0, Subsignal("d_p", Pins("34")), Subsignal("d_n", Pins("37")), @@ -43,6 +48,7 @@ _io = [ IOStandard("LVCMOS33") ), + # SPIFlash ("spiflash", 0, Subsignal("cs_n", Pins("16"), IOStandard("LVCMOS33")), Subsignal("clk", Pins("15"), IOStandard("LVCMOS33")), @@ -57,6 +63,8 @@ _io = [ Subsignal("clk", Pins("15"), IOStandard("LVCMOS33")), Subsignal("dq", Pins("14 17 18 19"), IOStandard("LVCMOS33")), ), + + # I2C ("i2c", 0, Subsignal("scl", Pins("12"), IOStandard("LVCMOS18")), Subsignal("sda", Pins("20"), IOStandard("LVCMOS18")), diff --git a/litex_boards/platforms/fomu_hacker.py b/litex_boards/platforms/fomu_hacker.py index a2c465e..37ae8a6 100644 --- a/litex_boards/platforms/fomu_hacker.py +++ b/litex_boards/platforms/fomu_hacker.py @@ -14,8 +14,10 @@ from litex.build.lattice.programmer import IceStormProgrammer # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst ("clk48", 0, Pins("F5"), IOStandard("LVCMOS33")), + # Leds ("user_led_n", 0, Pins("A5"), IOStandard("LVCMOS33")), ("rgb_led", 0, Subsignal("r", Pins("C5")), @@ -24,11 +26,13 @@ _io = [ IOStandard("LVCMOS33") ), + # Buttons ("user_touch_n", 0, Pins("F4"), IOStandard("LVCMOS33")), ("user_touch_n", 1, Pins("E5"), IOStandard("LVCMOS33")), ("user_touch_n", 2, Pins("E4"), IOStandard("LVCMOS33")), ("user_touch_n", 3, Pins("F2"), IOStandard("LVCMOS33")), + # USB ("usb", 0, Subsignal("d_p", Pins("A4")), Subsignal("d_n", Pins("A2")), @@ -36,13 +40,13 @@ _io = [ IOStandard("LVCMOS33") ), + # SPIFlash ("spiflash", 0, Subsignal("cs_n", Pins("C1"), IOStandard("LVCMOS33")), Subsignal("clk", Pins("D1"), IOStandard("LVCMOS33")), Subsignal("mosi", Pins("F1"), IOStandard("LVCMOS33")), Subsignal("miso", Pins("E1"), IOStandard("LVCMOS33")), ), - ("spiflash4x", 0, Subsignal("cs_n", Pins("C1"), IOStandard("LVCMOS33")), Subsignal("clk", Pins("D1"), IOStandard("LVCMOS33")), diff --git a/litex_boards/platforms/fomu_pvt.py b/litex_boards/platforms/fomu_pvt.py index 4c99c9f..4ccc8dc 100644 --- a/litex_boards/platforms/fomu_pvt.py +++ b/litex_boards/platforms/fomu_pvt.py @@ -15,8 +15,10 @@ from litex.build.lattice.programmer import IceStormProgrammer # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst ("clk48", 0, Pins("F4"), IOStandard("LVCMOS33")), + # Leds ("user_led_n", 0, Pins("A5"), IOStandard("LVCMOS33")), ("rgb_led", 0, Subsignal("r", Pins("C5")), @@ -25,11 +27,13 @@ _io = [ IOStandard("LVCMOS33") ), + # Buttons ("user_touch_n", 0, Pins("E4"), IOStandard("LVCMOS33")), ("user_touch_n", 1, Pins("D5"), IOStandard("LVCMOS33")), ("user_touch_n", 2, Pins("E5"), IOStandard("LVCMOS33")), ("user_touch_n", 3, Pins("F5"), IOStandard("LVCMOS33")), + # USB ("usb", 0, Subsignal("d_p", Pins("A1")), Subsignal("d_n", Pins("A2")), @@ -37,6 +41,7 @@ _io = [ IOStandard("LVCMOS33") ), + # SPIFlash ("spiflash", 0, Subsignal("cs_n", Pins("C1"), IOStandard("LVCMOS33")), Subsignal("clk", Pins("D1"), IOStandard("LVCMOS33")), diff --git a/litex_boards/platforms/genesys2.py b/litex_boards/platforms/genesys2.py index 340cdb9..a2eeb17 100644 --- a/litex_boards/platforms/genesys2.py +++ b/litex_boards/platforms/genesys2.py @@ -11,6 +11,14 @@ from litex.build.openocd import OpenOCD # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst + ("clk200", 0, + Subsignal("p", Pins("AD12"), IOStandard("LVDS")), + Subsignal("n", Pins("AD11"), IOStandard("LVDS")) + ), + ("cpu_reset_n", 0, Pins("R19"), IOStandard("LVCMOS33")), + + # Leds ("user_led", 0, Pins("T28"), IOStandard("LVCMOS33")), ("user_led", 1, Pins("V19"), IOStandard("LVCMOS33")), ("user_led", 2, Pins("U30"), IOStandard("LVCMOS33")), @@ -20,14 +28,14 @@ _io = [ ("user_led", 6, Pins("W24"), IOStandard("LVCMOS33")), ("user_led", 7, Pins("W23"), IOStandard("LVCMOS33")), - ("cpu_reset_n", 0, Pins("R19"), IOStandard("LVCMOS33")), - + # Buttons ("user_btn_c", 0, Pins("E18"), IOStandard("LVCMOS33")), ("user_btn_d", 0, Pins("M19"), IOStandard("LVCMOS33")), ("user_btn_l", 0, Pins("M20"), IOStandard("LVCMOS33")), ("user_btn_r", 0, Pins("C19"), IOStandard("LVCMOS33")), ("user_btn_u", 0, Pins("B19"), IOStandard("LVCMOS33")), + # Switches ("user_sw", 0, Pins("G19"), IOStandard("LVCMOS12")), ("user_sw", 1, Pins("G25"), IOStandard("LVCMOS12")), ("user_sw", 2, Pins("H24"), IOStandard("LVCMOS12")), @@ -37,17 +45,14 @@ _io = [ ("user_sw", 6, Pins("P26"), IOStandard("LVCMOS33")), ("user_sw", 7, Pins("P27"), IOStandard("LVCMOS33")), - ("clk200", 0, - Subsignal("p", Pins("AD12"), IOStandard("LVDS")), - Subsignal("n", Pins("AD11"), IOStandard("LVDS")) - ), - + # Serial ("serial", 0, Subsignal("tx", Pins("Y23")), Subsignal("rx", Pins("Y20")), IOStandard("LVCMOS33") ), + # USB FIFO ("usb_fifo", 0, # Can be used when FT2232H's Channel A configured to ASYNC FIFO 245 mode Subsignal("data", Pins("AD27 W27 W28 W29 Y29 Y28 AA28 AA26")), Subsignal("rxf_n", Pins("AB29")), @@ -61,14 +66,7 @@ _io = [ IOStandard("LVCMOS33"), ), - ("sdcard", 0, - Subsignal("clk", Pins("R28")), - Subsignal("cmd", Pins("R29"), Misc("PULLUP True")), - Subsignal("data", Pins("R26 R30 P29 T30"), Misc("PULLUP True")), - Misc("SLEW=FAST"), - IOStandard("LVCMOS33") - ), - + # SDCard ("spisdcard", 0, Subsignal("clk", Pins("R28")), Subsignal("cs_n", Pins("T30")), @@ -77,7 +75,16 @@ _io = [ Misc("SLEW=FAST"), IOStandard("LVCMOS33") ), + ("sdcard", 0, + Subsignal("clk", Pins("R28")), + Subsignal("cmd", Pins("R29"), Misc("PULLUP True")), + Subsignal("data", Pins("R26 R30 P29 T30"), Misc("PULLUP True")), + Misc("SLEW=FAST"), + IOStandard("LVCMOS33") + ), + + # DDR3 SDRAM ("ddram", 0, Subsignal("a", Pins( "AC12 AE8 AD8 AC10 AD9 AA13 AA10 AA11", @@ -109,6 +116,7 @@ _io = [ Misc("VCCAUX_IO=HIGH") ), + # RGMII Ethernet ("eth_clocks", 0, Subsignal("tx", Pins("AE10")), Subsignal("rx", Pins("AG10")), diff --git a/litex_boards/platforms/hadbadge.py b/litex_boards/platforms/hadbadge.py index 979c99e..cf4726a 100644 --- a/litex_boards/platforms/hadbadge.py +++ b/litex_boards/platforms/hadbadge.py @@ -13,18 +13,21 @@ from litex.build.lattice import LatticePlatform # IOs ---------------------------------------------------------------------------------------------- _io = [ - ("clk8", 0, Pins("U18"), IOStandard("LVCMOS33")), - + # Clk / Rst + ("clk8", 0, Pins("U18"), IOStandard("LVCMOS33")), ("programn", 0, Pins("R1"), IOStandard("LVCMOS33")), + # Leds + ("led", 0, Pins("E3 D3 C3 C4 C2 B1 B20 B19 A18 K20 K19"), IOStandard("LVCMOS33")), # Anodes + ("led", 1, Pins("P19 L18 K18"), IOStandard("LVCMOS33")), # Cathodes via FET + + # Serial ("serial", 0, Subsignal("rx", Pins("U2"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")), Subsignal("tx", Pins("U1"), IOStandard("LVCMOS33")), ), - ("led", 0, Pins("E3 D3 C3 C4 C2 B1 B20 B19 A18 K20 K19"), IOStandard("LVCMOS33")), # Anodes - ("led", 1, Pins("P19 L18 K18"), IOStandard("LVCMOS33")), # Cathodes via FET - + # USB ("usb", 0, Subsignal("d_p", Pins("F3")), Subsignal("d_n", Pins("G3")), @@ -33,6 +36,7 @@ _io = [ IOStandard("LVCMOS33") ), + # KeyPad ("keypad", 0, Subsignal("left", Pins("G2"), Misc("PULLMODE=UP")), Subsignal("right", Pins("F2"), Misc("PULLMODE=UP")), @@ -44,6 +48,7 @@ _io = [ Subsignal("b", Pins("E2"), Misc("PULLMODE=UP")), ), + # HDMI ("hdmi_out", 0, Subsignal("clk_p", Pins("P20"), Inverted(), IOStandard("TMDS_33")), Subsignal("clk_n", Pins("R20"), Inverted(), IOStandard("TMDS_33")), @@ -58,6 +63,7 @@ _io = [ Misc("DRIVE=4"), ), + # LCD ("lcd", 0, Subsignal("db", Pins( "J3 H1 K4 J1 K3 K2 L4 K1", @@ -74,6 +80,7 @@ _io = [ IOStandard("LVCMOS33") ), + # SPIFlash ("spiflash", 0, # Clock needs to be accessed through USRMCLK Subsignal("cs_n", Pins("R2")), Subsignal("mosi", Pins("W2")), @@ -82,13 +89,13 @@ _io = [ Subsignal("hold", Pins("W1")), IOStandard("LVCMOS33") ), - ("spiflash4x", 0, # Clock needs to be accessed through USRMCLK Subsignal("cs_n", Pins("R2")), Subsignal("dq", Pins("W2 V2 Y2 W1")), IOStandard("LVCMOS33") ), + # SPIRam ("spiram4x", 0, Subsignal("cs_n", Pins("D20")), Subsignal("clk", Pins("E20")), @@ -102,6 +109,22 @@ _io = [ IOStandard("LVCMOS33"), Misc("SLEWRATE=SLOW") ), + # SDR SDRAM + ("sdram_clock", 0, Pins("D11"), IOStandard("LVCMOS33")), + ("sdram", 0, + Subsignal("a", Pins("A8 D9 C9 B9 C14 E17 A12 B12 H17 G18 B8 A11 B11")), + Subsignal("dq", Pins("C5 B5 A5 C6 B10 C10 D10 A9")), + Subsignal("we_n", Pins("B6")), + Subsignal("ras_n", Pins("D6")), + Subsignal("cas_n", Pins("A6")), + Subsignal("cs_n", Pins("C7")), + Subsignal("cke", Pins("C11")), + Subsignal("ba", Pins("A7 C8")), + Subsignal("dm", Pins("A10")), + IOStandard("LVCMOS33"), Misc("SLEWRATE=FAST") + ), + + # SAO ("sao", 0, Subsignal("sda", Pins("B3")), Subsignal("scl", Pins("B2")), @@ -109,7 +132,6 @@ _io = [ Subsignal("drm", Pins("A4")), IOStandard("LVCMOS33"), ), - ("sao", 1, Subsignal("sda", Pins("A16")), Subsignal("scl", Pins("B17")), @@ -118,6 +140,7 @@ _io = [ IOStandard("LVCMOS33"), ), + # Test Points ("testpts", 0, Subsignal("a1", Pins("A15")), Subsignal("a2", Pins("C16")), @@ -129,22 +152,10 @@ _io = [ Subsignal("b4", Pins("B13")), IOStandard("LVCMOS33"), ), - - ("sdram_clock", 0, Pins("D11"), IOStandard("LVCMOS33")), - ("sdram", 0, - Subsignal("a", Pins("A8 D9 C9 B9 C14 E17 A12 B12 H17 G18 B8 A11 B11")), - Subsignal("dq", Pins("C5 B5 A5 C6 B10 C10 D10 A9")), - Subsignal("we_n", Pins("B6")), - Subsignal("ras_n", Pins("D6")), - Subsignal("cas_n", Pins("A6")), - Subsignal("cs_n", Pins("C7")), - Subsignal("cke", Pins("C11")), - Subsignal("ba", Pins("A7 C8")), - Subsignal("dm", Pins("A10")), - IOStandard("LVCMOS33"), Misc("SLEWRATE=FAST") - ), ] +# Connectors --------------------------------------------------------------------------------------- + _connectors = [ ("pmod", "A15 C16 A14 D16 B15 C15 A13 B13"), ("genio", "C5 B5 A5 C6 B6 A6 D6 C7 ", # 0-7 @@ -153,6 +164,8 @@ _connectors = [ "G18 H17 B12 A12 E17 C14"), # 24-29 ] +# PMODs -------------------------------------------------------------------------------------------- + _pmod_gpio = [ ("pmod_gpio", 0, Subsignal("p0", Pins("pmod:0")), @@ -167,6 +180,8 @@ _pmod_gpio = [ ), ] +# Generic IOs -------------------------------------------------------------------------------------- + _genio_gpio = [ ("genio_gpio", 0, Subsignal("p0", Pins("genio:0")), diff --git a/litex_boards/platforms/icebreaker.py b/litex_boards/platforms/icebreaker.py index 67dd392..af93c52 100644 --- a/litex_boards/platforms/icebreaker.py +++ b/litex_boards/platforms/icebreaker.py @@ -16,19 +16,27 @@ from litex.build.lattice.programmer import IceStormProgrammer # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst + ("clk12", 0, Pins("35"), IOStandard("LVCMOS33")) + + # Leds ("user_led_n", 0, Pins("11"), IOStandard("LVCMOS33")), ("user_led_n", 1, Pins("37"), IOStandard("LVCMOS33")), - # Color-specific aliases - ("user_ledr_n", 0, Pins("11"), IOStandard("LVCMOS33")), - ("user_ledg_n", 0, Pins("37"), IOStandard("LVCMOS33")), + + ("user_ledr_n", 0, Pins("11"), IOStandard("LVCMOS33")), # Color-specific alias + ("user_ledg_n", 0, Pins("37"), IOStandard("LVCMOS33")), # Color-specific alias + + # Button ("user_btn_n", 0, Pins("10"), IOStandard("LVCMOS33")), + # Serial ("serial", 0, Subsignal("rx", Pins("6")), Subsignal("tx", Pins("9"), Misc("PULLUP")), IOStandard("LVCMOS33") ), + # SPIFlash ("spiflash", 0, Subsignal("cs_n", Pins("16"), IOStandard("LVCMOS33")), Subsignal("clk", Pins("15"), IOStandard("LVCMOS33")), @@ -37,14 +45,11 @@ _io = [ Subsignal("wp", Pins("12"), IOStandard("LVCMOS33")), Subsignal("hold", Pins("13"), IOStandard("LVCMOS33")), ), - ("spiflash4x", 0, Subsignal("cs_n", Pins("16"), IOStandard("LVCMOS33")), Subsignal("clk", Pins("15"), IOStandard("LVCMOS33")), Subsignal("dq", Pins("14 17 12 13"), IOStandard("LVCMOS33")), ), - - ("clk12", 0, Pins("35"), IOStandard("LVCMOS33")) ] # Connectors --------------------------------------------------------------------------------------- diff --git a/litex_boards/platforms/kc705.py b/litex_boards/platforms/kc705.py index b2b25a6..924a3b2 100644 --- a/litex_boards/platforms/kc705.py +++ b/litex_boards/platforms/kc705.py @@ -13,6 +13,19 @@ from litex.build.openocd import OpenOCD # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst + ("clk200", 0, + Subsignal("p", Pins("AD12"), IOStandard("LVDS")), + Subsignal("n", Pins("AD11"), IOStandard("LVDS")) + ), + + ("clk156", 0, + Subsignal("p", Pins("K28"), IOStandard("LVDS_25")), + Subsignal("n", Pins("K29"), IOStandard("LVDS_25")) + ), + ("cpu_reset", 0, Pins("AB7"), IOStandard("LVCMOS15")), + + # Leds ("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")), ("user_led", 1, Pins("AA8"), IOStandard("LVCMOS15")), ("user_led", 2, Pins("AC9"), IOStandard("LVCMOS15")), @@ -22,19 +35,20 @@ _io = [ ("user_led", 6, Pins("E18"), IOStandard("LVCMOS25")), ("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")), - ("cpu_reset", 0, Pins("AB7"), IOStandard("LVCMOS15")), - + # Buttons ("user_btn_c", 0, Pins("G12"), IOStandard("LVCMOS25")), ("user_btn_n", 0, Pins("AA12"), IOStandard("LVCMOS15")), ("user_btn_s", 0, Pins("AB12"), IOStandard("LVCMOS15")), ("user_btn_w", 0, Pins("AC6"), IOStandard("LVCMOS15")), ("user_btn_e", 0, Pins("AG5"), IOStandard("LVCMOS15")), + # Switches ("user_dip_btn", 0, Pins("Y29"), IOStandard("LVCMOS25")), ("user_dip_btn", 1, Pins("W29"), IOStandard("LVCMOS25")), ("user_dip_btn", 2, Pins("AA28"), IOStandard("LVCMOS25")), ("user_dip_btn", 3, Pins("Y28"), IOStandard("LVCMOS25")), + # SMA ("user_sma_clock", 0, Subsignal("p", Pins("L25"), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")), @@ -43,25 +57,16 @@ _io = [ ), ("user_sma_clock_p", 0, Pins("L25"), IOStandard("LVCMOS25")), ("user_sma_clock_n", 0, Pins("K25"), IOStandard("LVCMOS25")), - ("user_sma_gpio_p", 0, Pins("Y23"), IOStandard("LVCMOS25")), ("user_sma_gpio_n", 0, Pins("Y24"), IOStandard("LVCMOS25")), - ("clk200", 0, - Subsignal("p", Pins("AD12"), IOStandard("LVDS")), - Subsignal("n", Pins("AD11"), IOStandard("LVDS")) - ), - - ("clk156", 0, - Subsignal("p", Pins("K28"), IOStandard("LVDS_25")), - Subsignal("n", Pins("K29"), IOStandard("LVDS_25")) - ), - + # I2C ("i2c", 0, Subsignal("scl", Pins("K21")), Subsignal("sda", Pins("L21")), IOStandard("LVCMOS25")), + # Serial ("serial", 0, Subsignal("cts", Pins("L27")), Subsignal("rts", Pins("K23")), @@ -70,56 +75,7 @@ _io = [ IOStandard("LVCMOS25") ), - ("spiflash", 0, # clock needs to be accessed through STARTUPE2 - Subsignal("cs_n", Pins("U19")), - Subsignal("dq", Pins("P24", "R25", "R20", "R21")), - IOStandard("LVCMOS25") - ), - - ("sdcard", 0, - Subsignal("clk", Pins("AB23")), - Subsignal("cmd", Pins("AB22"), Misc("PULLUP True")), - Subsignal("data", Pins("AC20 AA23 AA22 AC21"), Misc("PULLUP True")), - Misc("SLEW=FAST"), - IOStandard("LVCMOS25") - ), - - ("spisdcard", 0, - Subsignal("clk", Pins("AB23")), - Subsignal("cs_n", Pins("AC21")), - Subsignal("mosi", Pins("AB22"), Misc("PULLUP")), - Subsignal("miso", Pins("AC20"), Misc("PULLUP")), - Misc("SLEW=FAST"), - IOStandard("LVCMOS25") - ), - - ("lcd", 0, - Subsignal("db", Pins("AA13 AA10 AA11 Y10")), - Subsignal("e", Pins("AB10")), - Subsignal("rs", Pins("Y11")), - Subsignal("rw", Pins("AB13")), - IOStandard("LVCMOS15")), - - ("rotary", 0, - Subsignal("a", Pins("Y26")), - Subsignal("b", Pins("Y25")), - Subsignal("push", Pins("AA26")), - IOStandard("LVCMOS25")), - - ("hdmi", 0, - Subsignal("d", Pins( - "B23 A23 E23 D23 F25 E25 E24 D24", - "F26 E26 G23 G24 J19 H19 L17 L18", - "K19 K20")), - Subsignal("de", Pins("H17")), - Subsignal("clk", Pins("K18")), - Subsignal("vsync", Pins("H20")), - Subsignal("hsync", Pins("J18")), - Subsignal("int", Pins("AH24")), - Subsignal("spdif", Pins("J17")), - Subsignal("spdif_out", Pins("G20")), - IOStandard("LVCMOS25")), - + # DDR3 SDRAM ("ddram", 0, Subsignal("a", Pins( "AH12 AG13 AG12 AF12 AJ12 AJ13 AJ14 AH14", @@ -156,42 +112,31 @@ _io = [ Misc("VCCAUX_IO=HIGH") ), - ("ddram_dual_rank", 0, - Subsignal("a", Pins( - "AH12 AG13 AG12 AF12 AJ12 AJ13 AJ14 AH14", - "AK13 AK14 AF13 AE13 AJ11 AH11 AK10 AK11"), - IOStandard("SSTL15")), - Subsignal("ba", Pins("AH9 AG9 AK9"), IOStandard("SSTL15")), - Subsignal("ras_n", Pins("AD9"), IOStandard("SSTL15")), - Subsignal("cas_n", Pins("AC11"), IOStandard("SSTL15")), - Subsignal("we_n", Pins("AE9"), IOStandard("SSTL15")), - Subsignal("cs_n", Pins("AC12 AE8"), IOStandard("SSTL15")), - Subsignal("dm", Pins( - "Y16 AB17 AF17 AE16 AK5 AJ3 AF6 AC7"), - IOStandard("SSTL15")), - Subsignal("dq", Pins( - "AA15 AA16 AC14 AD14 AA17 AB15 AE15 Y15", - "AB19 AD16 AC19 AD17 AA18 AB18 AE18 AD18", - "AG19 AK19 AG18 AF18 AH19 AJ19 AE19 AD19", - "AK16 AJ17 AG15 AF15 AH17 AG14 AH15 AK15", - "AK8 AK6 AG7 AF7 AF8 AK4 AJ8 AJ6", - "AH5 AH6 AJ2 AH2 AH4 AJ4 AK1 AJ1", - "AF1 AF2 AE4 AE3 AF3 AF5 AE1 AE5", - "AC1 AD3 AC4 AC5 AE6 AD6 AC2 AD4"), - IOStandard("SSTL15_T_DCI")), - Subsignal("dqs_p", Pins("AC16 Y19 AJ18 AH16 AH7 AG2 AG4 AD2"), - IOStandard("DIFF_SSTL15")), - Subsignal("dqs_n", Pins("AC15 Y18 AK18 AJ16 AJ7 AH1 AG3 AD1"), - IOStandard("DIFF_SSTL15")), - Subsignal("clk_p", Pins("AG10 AE11"), IOStandard("DIFF_SSTL15")), - Subsignal("clk_n", Pins("AH10 AF11"), IOStandard("DIFF_SSTL15")), - Subsignal("cke", Pins("AF10 AE10"), IOStandard("SSTL15")), - Subsignal("odt", Pins("AD8 AC10"), IOStandard("SSTL15")), - Subsignal("reset_n", Pins("AK3"), IOStandard("LVCMOS15")), + # SPIFlash + ("spiflash", 0, # clock needs to be accessed through STARTUPE2 + Subsignal("cs_n", Pins("U19")), + Subsignal("dq", Pins("P24", "R25", "R20", "R21")), + IOStandard("LVCMOS25") + ), + + # SDCard + ("spisdcard", 0, + Subsignal("clk", Pins("AB23")), + Subsignal("cs_n", Pins("AC21")), + Subsignal("mosi", Pins("AB22"), Misc("PULLUP")), + Subsignal("miso", Pins("AC20"), Misc("PULLUP")), Misc("SLEW=FAST"), - Misc("VCCAUX_IO=HIGH") + IOStandard("LVCMOS25") + ), + ("sdcard", 0, + Subsignal("clk", Pins("AB23")), + Subsignal("cmd", Pins("AB22"), Misc("PULLUP True")), + Subsignal("data", Pins("AC20 AA23 AA22 AC21"), Misc("PULLUP True")), + Misc("SLEW=FAST"), + IOStandard("LVCMOS25") ), + # GMII Ethernet ("eth_clocks", 0, Subsignal("tx", Pins("M28")), Subsignal("gtx", Pins("K30")), @@ -214,6 +159,40 @@ _io = [ IOStandard("LVCMOS25") ), + # LCD + ("lcd", 0, + Subsignal("db", Pins("AA13 AA10 AA11 Y10")), + Subsignal("e", Pins("AB10")), + Subsignal("rs", Pins("Y11")), + Subsignal("rw", Pins("AB13")), + IOStandard("LVCMOS15") + ), + + # Rotary Encoder + ("rotary", 0, + Subsignal("a", Pins("Y26")), + Subsignal("b", Pins("Y25")), + Subsignal("push", Pins("AA26")), + IOStandard("LVCMOS25") + ), + + # HDMI + ("hdmi", 0, + Subsignal("d", Pins( + "B23 A23 E23 D23 F25 E25 E24 D24", + "F26 E26 G23 G24 J19 H19 L17 L18", + "K19 K20")), + Subsignal("de", Pins("H17")), + Subsignal("clk", Pins("K18")), + Subsignal("vsync", Pins("H20")), + Subsignal("hsync", Pins("J18")), + Subsignal("int", Pins("AH24")), + Subsignal("spdif", Pins("J17")), + Subsignal("spdif_out", Pins("G20")), + IOStandard("LVCMOS25") + ), + + # PCIe ("pcie_x1", 0, Subsignal("rst_n", Pins("G25"), IOStandard("LVCMOS25")), Subsignal("clk_p", Pins("U8")), @@ -251,13 +230,13 @@ _io = [ Subsignal("tx_n", Pins("L3 M1 N3 P1 T1 U3 V1 Y1")) ), - ("vadj_on_b", 0, Pins("J27"), IOStandard("LVCMOS25")), - + # SGMII Clk ("sgmii_clock", 0, Subsignal("p", Pins("G8")), Subsignal("n", Pins("G7")) ), + # SMA ("user_sma_mgt_refclk", 0, Subsignal("p", Pins("J8")), Subsignal("n", Pins("J7")) @@ -270,6 +249,8 @@ _io = [ Subsignal("p", Pins("K6")), Subsignal("n", Pins("K5")) ), + + # SFP ("sfp", 0, # inverted prior to HW rev 1.1 Subsignal("txp", Pins("H2")), Subsignal("txn", Pins("H1")), @@ -287,6 +268,7 @@ _io = [ ("sfp_tx_disable_n", 0, Pins("Y20"), IOStandard("LVCMOS25")), ("sfp_rx_los", 0, Pins("P19"), IOStandard("LVCMOS25")), + # SI5324 ("si5324", 0, Subsignal("rst_n", Pins("AE20"), IOStandard("LVCMOS25")), Subsignal("int", Pins("AG24"), IOStandard("LVCMOS25")) @@ -299,6 +281,9 @@ _io = [ Subsignal("p", Pins("L8")), Subsignal("n", Pins("L7")) ), + + # Others + ("vadj_on_b", 0, Pins("J27"), IOStandard("LVCMOS25")), ] # Connectors --------------------------------------------------------------------------------------- diff --git a/litex_boards/platforms/kcu105.py b/litex_boards/platforms/kcu105.py index 9ab77a7..98e831a 100644 --- a/litex_boards/platforms/kcu105.py +++ b/litex_boards/platforms/kcu105.py @@ -10,6 +10,19 @@ from litex.build.xilinx import XilinxPlatform, VivadoProgrammer # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst + ("clk125", 0, + Subsignal("p", Pins("G10"), IOStandard("LVDS")), + Subsignal("n", Pins("F10"), IOStandard("LVDS")) + ), + + ("clk300", 0, + Subsignal("p", Pins("AK17"), IOStandard("DIFF_SSTL12")), + Subsignal("n", Pins("AK16"), IOStandard("DIFF_SSTL12")) + ), + ("cpu_reset", 0, Pins("AN8"), IOStandard("LVCMOS18")), + + # Leds ("user_led", 0, Pins("AP8"), IOStandard("LVCMOS18")), ("user_led", 1, Pins("H23"), IOStandard("LVCMOS18")), ("user_led", 2, Pins("P20"), IOStandard("LVCMOS18")), @@ -19,26 +32,26 @@ _io = [ ("user_led", 6, Pins("R23"), IOStandard("LVCMOS18")), ("user_led", 7, Pins("P23"), IOStandard("LVCMOS18")), - ("cpu_reset", 0, Pins("AN8"), IOStandard("LVCMOS18")), - + # Buttons ("user_btn_c", 0, Pins("AE10"), IOStandard("LVCMOS18")), ("user_btn_n", 0, Pins("AD10"), IOStandard("LVCMOS18")), ("user_btn_s", 0, Pins("AF8"), IOStandard("LVCMOS18")), ("user_btn_w", 0, Pins("AF9"), IOStandard("LVCMOS18")), ("user_btn_e", 0, Pins("AE8"), IOStandard("LVCMOS18")), + # Switches ("user_dip_btn", 0, Pins("AN16"), IOStandard("LVCMOS12")), ("user_dip_btn", 1, Pins("AN19"), IOStandard("LVCMOS12")), ("user_dip_btn", 2, Pins("AP18"), IOStandard("LVCMOS12")), ("user_dip_btn", 3, Pins("AN14"), IOStandard("LVCMOS12")), + # SMA ("user_sma_clock", 0, Subsignal("p", Pins("D23"), IOStandard("LVDS")), Subsignal("n", Pins("C23"), IOStandard("LVDS")) ), ("user_sma_clock_p", 0, Pins("D23"), IOStandard("LVCMOS18")), ("user_sma_clock_n", 0, Pins("C23"), IOStandard("LVCMOS18")), - ("user_sma_gpio", 0, Subsignal("p", Pins("H27"), IOStandard("LVDS")), Subsignal("n", Pins("G27"), IOStandard("LVDS")) @@ -46,22 +59,14 @@ _io = [ ("user_sma_gpio_p", 0, Pins("H27"), IOStandard("LVCMOS18")), ("user_sma_gpio_n", 0, Pins("G27"), IOStandard("LVCMOS18")), - ("clk125", 0, - Subsignal("p", Pins("G10"), IOStandard("LVDS")), - Subsignal("n", Pins("F10"), IOStandard("LVDS")) - ), - - ("clk300", 0, - Subsignal("p", Pins("AK17"), IOStandard("DIFF_SSTL12")), - Subsignal("n", Pins("AK16"), IOStandard("DIFF_SSTL12")) - ), - + # I2C ("i2c", 0, Subsignal("scl", Pins("J24")), Subsignal("sda", Pins("J25")), IOStandard("LVCMOS18") ), + # Serial ("serial", 0, Subsignal("cts", Pins("L23")), Subsignal("rts", Pins("K27")), @@ -70,26 +75,19 @@ _io = [ IOStandard("LVCMOS18") ), + # SPIFlash ("spiflash", 0, # clock needs to be accessed through primitive Subsignal("cs_n", Pins("U7")), Subsignal("dq", Pins("AC7 AB7 AA7 Y7")), IOStandard("LVCMOS18") ), - ("spiflash", 1, # clock needs to be accessed through primitive Subsignal("cs_n", Pins("G26")), Subsignal("dq", Pins("M20 L20 R21 R22")), IOStandard("LVCMOS18") ), - ("sdcard", 0, - Subsignal("clk", Pins("AL10")), - Subsignal("cmd", Pins("AD9"), Misc("PULLUP True")), - Subsignal("data", Pins("AP9 AN9 AH9 AH8"), Misc("PULLUP True")), - Misc("SLEW=FAST"), - IOStandard("LVCMOS18") - ), - + # SDCard ("spisdcard", 0, Subsignal("clk", Pins("AL10")), Subsignal("cs_n", Pins("AH8")), @@ -98,7 +96,15 @@ _io = [ Misc("SLEW=FAST"), IOStandard("LVCMOS18") ), + ("sdcard", 0, + Subsignal("clk", Pins("AL10")), + Subsignal("cmd", Pins("AD9"), Misc("PULLUP True")), + Subsignal("data", Pins("AP9 AN9 AH9 AH8"), Misc("PULLUP True")), + Misc("SLEW=FAST"), + IOStandard("LVCMOS18") + ), + # Rotary Encoder ("rotary", 0, Subsignal("a", Pins("Y21")), Subsignal("b", Pins("AD26")), @@ -106,6 +112,7 @@ _io = [ IOStandard("LVCMOS18") ), + # HDMI ("hdmi", 0, Subsignal("d", Pins( "AK11 AP11 AP13 AN13 AN11 AM11 AN12 AM12", @@ -120,6 +127,7 @@ _io = [ IOStandard("LVCMOS18") ), + # DDR4 SDRAM ("ddram", 0, Subsignal("a", Pins( "AE17 AH17 AE18 AJ15 AG16 AL17 AK18 AG17", @@ -165,6 +173,7 @@ _io = [ Misc("SLEW=FAST"), ), + # PCIe ("pcie_x1", 0, Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")), Subsignal("clk_p", Pins("AB6")), @@ -174,7 +183,6 @@ _io = [ Subsignal("tx_p", Pins("AC4")), Subsignal("tx_n", Pins("AC3")) ), - ("pcie_x2", 0, Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")), Subsignal("clk_p", Pins("AB6")), @@ -184,7 +192,6 @@ _io = [ Subsignal("tx_p", Pins("AC4 AE4")), Subsignal("tx_n", Pins("AC3 AE3")) ), - ("pcie_x4", 0, Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")), Subsignal("clk_p", Pins("AB6")), @@ -194,7 +201,6 @@ _io = [ Subsignal("tx_p", Pins("AC4 AE4 AG4 AH6")), Subsignal("tx_n", Pins("AC3 AE3 AG3 AH5")) ), - ("pcie_x8", 0, Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")), Subsignal("clk_p", Pins("AB6")), @@ -205,16 +211,19 @@ _io = [ Subsignal("tx_n", Pins("AC3 AE3 AG3 AH5 AK5 AL3 AM5 AN3")) ), + # SGMII Clk ("sgmii_clock", 0, Subsignal("p", Pins("P26"), IOStandard("LVDS_25")), Subsignal("n", Pins("N26"), IOStandard("LVDS_25")) ), + # SI570 ("si570_refclk", 0, Subsignal("p", Pins("P6")), Subsignal("n", Pins("P5")) ), + # SMA ("user_sma_mgt_refclk", 0, Subsignal("p", Pins("V6")), Subsignal("n", Pins("V5")) @@ -228,6 +237,7 @@ _io = [ Subsignal("n", Pins("P1")) ), + # SFP ("sfp", 0, Subsignal("txp", Pins("U4")), Subsignal("txn", Pins("U3")), diff --git a/litex_boards/platforms/kx2.py b/litex_boards/platforms/kx2.py index 59ed2cc..aadf3e2 100644 --- a/litex_boards/platforms/kx2.py +++ b/litex_boards/platforms/kx2.py @@ -11,24 +11,27 @@ from litex.build.openocd import OpenOCD # IOs ---------------------------------------------------------------------------------------------- _io = [ - ("user_led", 0, Pins("U9"), IOStandard("LVCMOS15")), - ("user_led", 1, Pins("V12"), IOStandard("LVCMOS15")), - ("user_led", 2, Pins("V13"), IOStandard("LVCMOS15")), - ("user_led", 3, Pins("W13"), IOStandard("LVCMOS15")), - - ("cpu_reset_n", 0, Pins("G9"), IOStandard("LVCMOS25")), - + # Clk / Rst ("clk200", 0, Subsignal("p", Pins("AB11"), IOStandard("LVDS")), Subsignal("n", Pins("AC11"), IOStandard("LVDS")) ), + ("cpu_reset_n", 0, Pins("G9"), IOStandard("LVCMOS25")), + + # Leds + ("user_led", 0, Pins("U9"), IOStandard("LVCMOS15")), + ("user_led", 1, Pins("V12"), IOStandard("LVCMOS15")), + ("user_led", 2, Pins("V13"), IOStandard("LVCMOS15")), + ("user_led", 3, Pins("W13"), IOStandard("LVCMOS15")), + # Serial ("serial", 0, Subsignal("tx", Pins("W11")), Subsignal("rx", Pins("AB16")), IOStandard("LVCMOS15") # FIXME: LVCMOS15 or LVCMOS33? ), + # DDR3 SDRAM ("ddram", 0, Subsignal("a", Pins( "AE11 AF9 AD10 AB10 AA9 AB9 AA8 AC8", diff --git a/litex_boards/platforms/linsn_rv901t.py b/litex_boards/platforms/linsn_rv901t.py index d5d8bd6..a849cba 100644 --- a/litex_boards/platforms/linsn_rv901t.py +++ b/litex_boards/platforms/linsn_rv901t.py @@ -15,20 +15,20 @@ from litex.build.openocd import OpenOCD # IOs ---------------------------------------------------------------------------------------------- _io = [ - # clock + # Clk / Rst ("clk25", 0, Pins("M9"), IOStandard("LVCMOS33")), - # led + # Leds ("user_led", 0, Pins("F7"), IOStandard("LVCMOS33")), - # serial + # Serial ("serial", 0, Subsignal("tx", Pins("H5")), Subsignal("rx", Pins("G6")), IOStandard("LVCMOS33") ), - # ethernet + # RGMII Ethernet ("eth_clocks", 0, Subsignal("tx", Pins("D1")), Subsignal("rx", Pins("F1")), @@ -41,7 +41,6 @@ _io = [ Subsignal("tx_data", Pins("E3 E2 E1 F3")), IOStandard("LVCMOS33") ), - ("eth_clocks", 1, Subsignal("tx", Pins("J1")), Subsignal("rx", Pins("K3")), @@ -55,7 +54,7 @@ _io = [ IOStandard("LVCMOS33") ), - # sdram + # SDR SDRAM ("sdram_clock", 0, Pins("K11"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")), ("sdram_clock", 1, Pins("K12"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")), ("sdram", 0, diff --git a/litex_boards/platforms/logicbone.py b/litex_boards/platforms/logicbone.py index 1d4337a..4cd0470 100644 --- a/litex_boards/platforms/logicbone.py +++ b/litex_boards/platforms/logicbone.py @@ -16,15 +16,20 @@ from litex.build.dfu import DFUProg # IOs ---------------------------------------------------------------------------------------------- _io_rev0 = [ - ("refclk", 0, Pins("M19"), IOStandard("LVCMOS18")), - ("rst_n", 0, Pins("C17"), IOStandard("LVCMOS33")), - ("user_btn", 0, Pins("U2"), IOStandard("LVCMOS33")), + # Clk / Rst + ("clk25", 0, Pins("M19"), IOStandard("LVCMOS18")), + ("rst_n", 0, Pins("C17"), IOStandard("LVCMOS33")), + # Leds ("user_led", 0, Pins("D16"), IOStandard("LVCMOS33")), ("user_led", 1, Pins("C15"), IOStandard("LVCMOS33")), ("user_led", 2, Pins("C13"), IOStandard("LVCMOS33")), ("user_led", 3, Pins("B13"), IOStandard("LVCMOS33")), + # Buttons + ("user_btn", 0, Pins("U2"), IOStandard("LVCMOS33")), + + # DDR3 SDRAM ("ddram", 0, Subsignal("a", Pins( "D5 F4 B3 F3 E5 C3 C4 A5", @@ -52,6 +57,7 @@ _io_rev0 = [ Misc("SLEWRATE=FAST"), ), + # USB ("usb", 0, Subsignal("d_p", Pins("B12")), Subsignal("d_n", Pins("C12")), @@ -59,16 +65,13 @@ _io_rev0 = [ IOStandard("LVCMOS33") ), + # Serial ("serial", 0, Subsignal("rx", Pins("B6"), IOStandard("LVCMOS33")), Subsignal("tx", Pins("A7"), IOStandard("LVCMOS33")), ), - ("spiflash4x", 0, - Subsignal("cs_n", Pins("R2"), IOStandard("LVCMOS33")), - #Subsignal("clk", Pins("U3"), IOStandard("LVCMOS33")), # Note: CLK is bound using USRMCLK block - Subsignal("dq", Pins("W2 V2 Y2 W1"), IOStandard("LVCMOS33")), - ), + # SPIFlash ("spiflash", 0, Subsignal("cs_n", Pins("R2"), IOStandard("LVCMOS33")), #Subsignal("clk", Pins("U3"), IOStandard("LVCMOS33")), # Note: CLK is bound using USRMCLK block @@ -77,15 +80,13 @@ _io_rev0 = [ Subsignal("wp", Pins("Y2"), IOStandard("LVCMOS33")), Subsignal("hold", Pins("W1"), IOStandard("LVCMOS33")), ), - - ("sdcard", 0, - Subsignal("clk", Pins("E11")), - Subsignal("cmd", Pins("D15"), Misc("PULLMODE=UP")), - Subsignal("data", Pins("D13 E13 E15 E14"), Misc("PULLMODE=UP")), - Subsignal("cd", Pins("D14"), Misc("PULLMODE=UP")), - IOStandard("LVCMOS33"), Misc("SLEW=FAST") + ("spiflash4x", 0, + Subsignal("cs_n", Pins("R2"), IOStandard("LVCMOS33")), + #Subsignal("clk", Pins("U3"), IOStandard("LVCMOS33")), # Note: CLK is bound using USRMCLK block + Subsignal("dq", Pins("W2 V2 Y2 W1"), IOStandard("LVCMOS33")), ), + # SDCard ("spisdcard", 0, Subsignal("clk", Pins("E11")), Subsignal("mosi", Pins("D15"), Misc("PULLMODE=UP")), @@ -94,13 +95,22 @@ _io_rev0 = [ Misc("SLEW=FAST"), IOStandard("LVCMOS33"), ), + ("sdcard", 0, + Subsignal("clk", Pins("E11")), + Subsignal("cmd", Pins("D15"), Misc("PULLMODE=UP")), + Subsignal("data", Pins("D13 E13 E15 E14"), Misc("PULLMODE=UP")), + Subsignal("cd", Pins("D14"), Misc("PULLMODE=UP")), + IOStandard("LVCMOS33"), Misc("SLEW=FAST") + ), + # I2C ("i2c", 0, Subsignal("sda", Pins("V1")), Subsignal("scl", Pins("U1")), IOStandard("LVCMOS33") ), + # RGMII Ethernet ("eth_clocks", 0, Subsignal("tx", Pins("A15")), Subsignal("rx", Pins("B18")), @@ -179,7 +189,7 @@ _connectors_rev0 = [ # Platform ----------------------------------------------------------------------------------------- class Platform(LatticePlatform): - default_clk_name = "refclk" + default_clk_name = "clk25" default_clk_period = 1e9/25e6 def __init__(self, revision="rev0", device="45F", **kwargs): @@ -194,5 +204,5 @@ class Platform(LatticePlatform): def do_finalize(self, fragment): LatticePlatform.do_finalize(self, fragment) - self.add_period_constraint(self.lookup_request("refclk", loose=True), 1e9/25e6) + self.add_period_constraint(self.lookup_request("clk25", loose=True), 1e9/25e6) self.add_period_constraint(self.lookup_request("eth_clocks:rx", loose=True), 1e9/125e6) diff --git a/litex_boards/platforms/machxo3.py b/litex_boards/platforms/machxo3.py index 96042c5..84034f2 100644 --- a/litex_boards/platforms/machxo3.py +++ b/litex_boards/platforms/machxo3.py @@ -11,9 +11,11 @@ from litex.build.lattice.programmer import LatticeProgrammer # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst ("clk12", 0, Pins("C8"), IOStandard("LVCMOS33")), ("rst_n", 0, Pins("B3"), IOStandard("LVCMOS33")), + # Leds ("user_led", 0, Pins("H11"), IOStandard("LVCMOS33")), ("user_led", 1, Pins("J13"), IOStandard("LVCMOS33")), ("user_led", 2, Pins("J11"), IOStandard("LVCMOS33")), @@ -23,11 +25,13 @@ _io = [ ("user_led", 6, Pins("N15"), IOStandard("LVCMOS33")), ("user_led", 7, Pins("P16"), IOStandard("LVCMOS33")), + # Switches ("user_dip_btn", 0, Pins("N2"), IOStandard("LVCMOS33")), ("user_dip_btn", 1, Pins("P1"), IOStandard("LVCMOS33")), ("user_dip_btn", 2, Pins("M3"), IOStandard("LVCMOS33")), ("user_dip_btn", 3, Pins("N1"), IOStandard("LVCMOS33")), + # Serial ("serial", 0, Subsignal("tx", Pins("C11"), IOStandard("LVCMOS33")), Subsignal("rx", Pins("A11"), IOStandard("LVCMOS33")), diff --git a/litex_boards/platforms/marblemini.py b/litex_boards/platforms/marblemini.py index 20f6f1b..33c493c 100644 --- a/litex_boards/platforms/marblemini.py +++ b/litex_boards/platforms/marblemini.py @@ -20,9 +20,9 @@ from litex.build.openocd import OpenOCD # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst ("clk20_vcxo", 0, Pins("D17"), IOStandard("LVCMOS33")), ("clk20_vcxo_en", 0, Pins("E13"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")), # Set it to 1 to enable clk20_-vcxo. - ("mgt_clk", 0, Subsignal("p", Pins("F6")), Subsignal("n", Pins("E6")) @@ -33,6 +33,7 @@ _io = [ Subsignal("n", Pins("E10")) ), + # Serial ("serial", 0, Subsignal("rts", Pins("W9")), Subsignal("rx", Pins("U7")), @@ -40,6 +41,7 @@ _io = [ IOStandard("LVCMOS25") ), + # RGMII Ethernet ("eth_clocks", 0, Subsignal("tx", Pins("J15")), Subsignal("rx", Pins("L19")), @@ -52,8 +54,9 @@ _io = [ Subsignal("tx_ctl", Pins("J16")), Subsignal("tx_data", Pins("G15 G16 G13 H13")), IOStandard("LVCMOS25"), - ), + ), + # DDR3 SDRAM ("ddram", 0, Subsignal("a", Pins( "L6 M5 P6 K6 M1 M3 N2 M6", diff --git a/litex_boards/platforms/mercury_xu5.py b/litex_boards/platforms/mercury_xu5.py index e5d1721..719ef24 100644 --- a/litex_boards/platforms/mercury_xu5.py +++ b/litex_boards/platforms/mercury_xu5.py @@ -10,41 +10,42 @@ from litex.build.xilinx import XilinxPlatform, VivadoProgrammer # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst ("clk100", 0, Subsignal("n", Pins("AD4"), IOStandard("DIFF_SSTL12_DCI")), Subsignal("p", Pins("AD5"), IOStandard("DIFF_SSTL12_DCI")), ), - ("clk100_gtr", 0, Subsignal("p", Pins("C21"), IOStandard("DIFF_SSTL12")), Subsignal("n", Pins("C22"), IOStandard("DIFF_SSTL12")), ), - ("clk27_gtr", 0, Subsignal("p", Pins("A21"), IOStandard("DIFF_SSTL12")), Subsignal("n", Pins("A22"), IOStandard("DIFF_SSTL12")), ), - ("clk33", 0, Pins("AD4"), IOStandard("SSTL12")), - ("cpu_reset", 0, Pins("N19"), IOStandard("LVCMOS33")), + # Leds ("user_led", 0, Pins("H2"), IOStandard("LVCMOS18")), ("user_led", 1, Pins("P9"), IOStandard("LVCMOS18")), ("user_led", 2, Pins("K5"), IOStandard("LVCMOS18")), + # Serial ("serial", 0, Subsignal("rx", Pins("AA10")), # Module connector A: A60 (Meccury PE1: "IO B" connector 32) Subsignal("tx", Pins("AA11")), # Module connector A: A58 (Meccury PE1: "IO B" connector 31) IOStandard("LVCMOS33"), ), + # I2C ("i2c", 0, Subsignal("scl", Pins("D12")), Subsignal("sda", Pins("C12")), IOStandard("LVCMOS18") ), + # DDR4 SDRAM ("ddram", 0, Subsignal("a", Pins( "AC4 AC3 AB4 AB3 AB2 AC2 AB1 AC1", diff --git a/litex_boards/platforms/mimas_a7.py b/litex_boards/platforms/mimas_a7.py index 4e04ec8..9c8d966 100644 --- a/litex_boards/platforms/mimas_a7.py +++ b/litex_boards/platforms/mimas_a7.py @@ -12,6 +12,11 @@ from litex.build.openocd import OpenOCD # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst + ("clk100", 0, Pins("H4"), IOStandard("LVCMOS33")), + ("cpu_reset", 0, Pins("M2"), IOStandard("LVCMOS33")), + + # Leds ("user_led", 0, Pins("K17"), IOStandard("LVCMOS33")), ("user_led", 1, Pins("J17"), IOStandard("LVCMOS33")), ("user_led", 2, Pins("L14"), IOStandard("LVCMOS33")), @@ -21,6 +26,7 @@ _io = [ ("user_led", 6, Pins("M15"), IOStandard("LVCMOS33")), ("user_led", 7, Pins("M16"), IOStandard("LVCMOS33")), + # Switches ("user_sw", 0, Pins("B21"), IOStandard("LVCMOS33")), ("user_sw", 1, Pins("A21"), IOStandard("LVCMOS33")), ("user_sw", 2, Pins("E22"), IOStandard("LVCMOS33")), @@ -30,21 +36,20 @@ _io = [ ("user_sw", 6, Pins("G21"), IOStandard("LVCMOS33")), ("user_sw", 7, Pins("G22"), IOStandard("LVCMOS33")), + # Buttons ("user_btn", 0, Pins("P20"), IOStandard("LVCMOS33")), ("user_btn", 1, Pins("P19"), IOStandard("LVCMOS33")), ("user_btn", 2, Pins("P17"), IOStandard("LVCMOS33")), ("user_btn", 3, Pins("N17"), IOStandard("LVCMOS33")), - ("clk100", 0, Pins("H4"), IOStandard("LVCMOS33")), - - ("cpu_reset", 0, Pins("M2"), IOStandard("LVCMOS33")), - + # Serial ("serial", 0, # Can be used when FT2232H's Channel A configured to ASYNC Serial (UART) mode Subsignal("tx", Pins("Y21")), Subsignal("rx", Pins("Y22")), IOStandard("LVCMOS33") ), + # USB FIFO ("usb_fifo", 0, # Can be used when FT2232H's Channel A configured to ASYNC FIFO 245 mode Subsignal("data", Pins("Y22 Y21 AB22 AA21 AB21 AA20 AB20 AA18")), Subsignal("rxf_n", Pins("W21")), @@ -58,12 +63,7 @@ _io = [ IOStandard("LVCMOS33"), ), - ("spiflash4x", 0, - Subsignal("cs_n", Pins("T19")), - Subsignal("clk", Pins("L12")), - Subsignal("dq", Pins("P22", "R22", "P21", "R21")), - IOStandard("LVCMOS33") - ), + # SPIFlash ("spiflash", 0, Subsignal("cs_n", Pins("T19")), Subsignal("clk", Pins("L12")), @@ -73,7 +73,14 @@ _io = [ Subsignal("hold", Pins("R21")), IOStandard("LVCMOS33"), ), + ("spiflash4x", 0, + Subsignal("cs_n", Pins("T19")), + Subsignal("clk", Pins("L12")), + Subsignal("dq", Pins("P22", "R22", "P21", "R21")), + IOStandard("LVCMOS33") + ), + # DDR3 SDRAM ("ddram", 0, Subsignal("a", Pins( "U6 T5 Y6 T6 V2 T4 Y2 R2", @@ -100,12 +107,14 @@ _io = [ Misc("SLEW=FAST"), ), + # I2C EEPROM ("eeprom", 0, Subsignal("scl", Pins("N5")), Subsignal("sda", Pins("P6")), IOStandard("LVCMOS33") ), + # RGMII Ethernet ("eth_clocks", 0, Subsignal("tx", Pins("U20")), Subsignal("rx", Pins("W19")), @@ -123,6 +132,7 @@ _io = [ IOStandard("LVCMOS33") ), + # HDMI In ("hdmi_in", 0, Subsignal("clk_p", Pins("K4"), IOStandard("TMDS_33")), Subsignal("clk_n", Pins("J4"), IOStandard("TMDS_33")), @@ -139,6 +149,7 @@ _io = [ # Subsignal("txen", Pins("R3"), IOStandard("LVCMOS33")), # FIXME ), + # HDMI Out ("hdmi_out", 0, Subsignal("clk_p", Pins("L3"), IOStandard("TMDS_33")), Subsignal("clk_n", Pins("K3"), IOStandard("TMDS_33")), diff --git a/litex_boards/platforms/minispartan6.py b/litex_boards/platforms/minispartan6.py index 16a7065..8aecda7 100644 --- a/litex_boards/platforms/minispartan6.py +++ b/litex_boards/platforms/minispartan6.py @@ -11,6 +11,11 @@ from litex.build.xilinx.programmer import XC3SProg # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst + ("clk32", 0, Pins("J4"), IOStandard("LVCMOS33")), + ("clk50", 0, Pins("K3"), IOStandard("LVCMOS33")), + + # Leds ("user_led", 0, Pins("P11"), IOStandard("LVCMOS33")), ("user_led", 1, Pins("N9"), IOStandard("LVCMOS33")), ("user_led", 2, Pins("M9"), IOStandard("LVCMOS33")), @@ -20,14 +25,14 @@ _io = [ ("user_led", 6, Pins("P8"), IOStandard("LVCMOS33")), ("user_led", 7, Pins("P7"), IOStandard("LVCMOS33")), + # Switches ("user_sw", 0, Pins("L1"), IOStandard("LVCMOS33"), Misc("PULLUP")), ("user_sw", 1, Pins("L3"), IOStandard("LVCMOS33"), Misc("PULLUP")), ("user_sw", 2, Pins("L4"), IOStandard("LVCMOS33"), Misc("PULLUP")), ("user_sw", 3, Pins("L5"), IOStandard("LVCMOS33"), Misc("PULLUP")), - ("clk32", 0, Pins("J4"), IOStandard("LVCMOS33")), - ("clk50", 0, Pins("K3"), IOStandard("LVCMOS33")), + # SPIFlash ("spiflash", 0, Subsignal("cs_n", Pins("T3"), IOStandard("LVCMOS33")), Subsignal("clk", Pins("R11"), IOStandard("LVCMOS33")), @@ -35,6 +40,26 @@ _io = [ Subsignal("miso", Pins("P10"), IOStandard("LVCMOS33")) ), + # Serial + ("serial", 0, + Subsignal("tx", Pins("N6"), IOStandard("LVCMOS33")), # FTDI D1 + Subsignal("rx", Pins("M7"), IOStandard("LVCMOS33")) # FTDI D0 + ), + + # USB FIFO + ("usb_fifo", 0, + Subsignal("data", Pins("M7 N6 M6 P5 N5 P4 P2 P1")), + Subsignal("rxf_n", Pins("N3")), + Subsignal("txe_n", Pins("N1")), + Subsignal("rd_n", Pins("M1")), + Subsignal("wr_n", Pins("M2")), + Subsignal("siwua", Pins("M3")), + Misc("SLEW=FAST"), + Drive(8), + IOStandard("LVCMOS33"), + ), + + # ADC ("adc", 0, Subsignal("cs_n", Pins("F6"), IOStandard("LVCMOS33")), Subsignal("clk", Pins("G6"), IOStandard("LVCMOS33")), @@ -42,16 +67,13 @@ _io = [ Subsignal("miso", Pins("H5"), IOStandard("LVCMOS33")) ), - ("serial", 0, - Subsignal("tx", Pins("N6"), IOStandard("LVCMOS33")), # FTDI D1 - Subsignal("rx", Pins("M7"), IOStandard("LVCMOS33")) # FTDI D0 - ), - + # Audio ("audio", 0, Subsignal("a0", Pins("B8"), IOStandard("LVCMOS33")), Subsignal("a1", Pins("A8"), IOStandard("LVCMOS33")) ), + # SDR SDRAM ("sdram_clock", 0, Pins("G16"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")), ("sdram", 0, Subsignal("a", Pins( @@ -71,18 +93,7 @@ _io = [ IOStandard("LVCMOS33"), ), - ("usb_fifo", 0, - Subsignal("data", Pins("M7 N6 M6 P5 N5 P4 P2 P1")), - Subsignal("rxf_n", Pins("N3")), - Subsignal("txe_n", Pins("N1")), - Subsignal("rd_n", Pins("M1")), - Subsignal("wr_n", Pins("M2")), - Subsignal("siwua", Pins("M3")), - Misc("SLEW=FAST"), - Drive(8), - IOStandard("LVCMOS33"), - ), - + # SDCard ("spisdcard", 0, Subsignal("clk", Pins("L12")), Subsignal("mosi", Pins("K11"), Misc("PULLUP")), @@ -91,7 +102,6 @@ _io = [ Misc("SLEW=FAST"), IOStandard("LVCMOS33"), ), - ("sdcard", 0, Subsignal("data", Pins("M10 L10 J11 K12"), Misc("PULLUP")), Subsignal("cmd", Pins("K11"), Misc("PULLUP")), @@ -100,6 +110,7 @@ _io = [ IOStandard("LVCMOS33"), ), + # DVI In ("dvi_in", 0, Subsignal("clk_p", Pins("C9"), IOStandard("TMDS_33")), Subsignal("clk_n", Pins("A9"), IOStandard("TMDS_33")), @@ -109,6 +120,7 @@ _io = [ Subsignal("sda", Pins("B1"), IOStandard("LVCMOS33")) ), + # DVI Out ("dvi_out", 0, Subsignal("clk_p", Pins("B14"), IOStandard("TMDS_33")), Subsignal("clk_n", Pins("A14"), IOStandard("TMDS_33")), diff --git a/litex_boards/platforms/mist.py b/litex_boards/platforms/mist.py index 6dbffc4..2fa533b 100644 --- a/litex_boards/platforms/mist.py +++ b/litex_boards/platforms/mist.py @@ -11,12 +11,21 @@ from litex.build.altera.programmer import USBBlaster # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst ("clk27", 0, Pins("54")), ("clk27", 0, Pins("54")), + # Leds ("user_led", 0, Pins("7"), Misc("CURRENT_STRENGTH_NEW 4MA")), + # Serial + ("serial", 0, + Subsignal("tx", Pins("46")), + Subsignal("rx", Pins("31")), + ), + + # VGA ("vga", 0, Subsignal("r", Pins("135 137 141 142 143 144")), Subsignal("g", Pins("106 110 111 112 113 114")), @@ -26,17 +35,15 @@ _io = [ Misc("CURRENT_STRENGTH_NEW \"MAXIMUM CURRENT\""), ), + # Audio ("audio", 0, Subsignal("l", Pins("65")), Subsignal("r", Pins("80")), Misc("CURRENT_STRENGTH_NEW 4MA"), ), - ("serial", 0, - Subsignal("tx", Pins("46")), - Subsignal("rx", Pins("31")), - ), + # SPI ("spi", 0, Subsignal("do", Pins("105")), Subsignal("di", Pins("88")), @@ -46,8 +53,7 @@ _io = [ Subsignal("ss4", Pins("90")), ), - ("conf_data0", 0, Pins("13")), - + # SDR SDRAM ("sdram_clock", 0, Pins("43"), Misc("CURRENT_STRENGTH_NEW \"MAXIMUM CURRENT\""), IOStandard("3.3-V LVTTL")), ("sdram", 0, @@ -64,6 +70,9 @@ _io = [ Misc("FAST_OUTPUT_REGISTER ON"), Misc("CURRENT_STRENGTH_NEW \"MAXIMUM CURRENT\""), ), + + # Others + ("conf_data0", 0, Pins("13")), ] # Platform ----------------------------------------------------------------------------------------- diff --git a/litex_boards/platforms/nereid.py b/litex_boards/platforms/nereid.py index 2b4b965..800be55 100644 --- a/litex_boards/platforms/nereid.py +++ b/litex_boards/platforms/nereid.py @@ -12,26 +12,26 @@ from litex.build.openocd import OpenOCD # IOs ---------------------------------------------------------------------------------------------- _io = [ - # rgb led, active-low - ("rgb_led", 0, - Subsignal("r", Pins("J26")), - Subsignal("g", Pins("H26")), - Subsignal("b", Pins("G26")), - IOStandard("LVCMOS33"), - ), - + # Clk / Rst ("clk100", 0, Pins("F22"), IOStandard("LVCMOS33")), - ("clk150", 0, Subsignal("p", Pins("G24"), IOStandard("TMDS_33")), Subsignal("n", Pins("F24"), IOStandard("TMDS_33")) ), + ("cpu_reset", 0, Pins("C26"), IOStandard("LVCMOS33"), Misc("PULLDOWN=True")), # Active high, pulldown needed. - # Active-high CPU reset, pulldown needed - ("cpu_reset", 0, Pins("C26"), IOStandard("LVCMOS33"), Misc("PULLDOWN=True")), + # Leds (activive-low) + ("rgb_led", 0, + Subsignal("r", Pins("J26")), + Subsignal("g", Pins("H26")), + Subsignal("b", Pins("G26")), + IOStandard("LVCMOS33"), + ), - ("fan_pwm", 0, Pins("J25"), IOStandard("LVCMOS33")), + # FAN + ("fan", 0, Pins("J25"), IOStandard("LVCMOS33")), + # Serial ("serial", 0, Subsignal("tx", Pins("H22")), Subsignal("rx", Pins("K22")), @@ -41,6 +41,7 @@ _io = [ IOStandard("LVCMOS33") ), + # XADC ("xadc", 0, Subsignal("adc_p", Pins("C16 A18 B17")), Subsignal("adc_n", Pins("B16 A19 A17")), @@ -48,6 +49,7 @@ _io = [ Subsignal("v_n", Pins("P11")), ), + # DDR3 SDRAM ("ddram", 0, Subsignal("a", Pins( "AF7 AE7 AC7 AB7 AA7 AC8 AC9 AA9", @@ -83,46 +85,7 @@ _io = [ Misc("SLEW=FAST"), ), - ("ddram_dual_rank", 0, - Subsignal("a", Pins( - "AF7 AE7 AC7 AB7 AA7 AC8 AC9 AA9", - "AD8 V9 Y11 Y7 W10 Y8 Y10 W9"), - IOStandard("SSTL135")), - Subsignal("ba", Pins("AA8 AD9 AB9"), IOStandard("SSTL135")), - Subsignal("ras_n", Pins("AC13"), IOStandard("SSTL135")), - Subsignal("cas_n", Pins("AC12"), IOStandard("SSTL135")), - Subsignal("we_n", Pins("AA13"), IOStandard("SSTL135")), - Subsignal("cs_n", Pins("AB12 AA12"), IOStandard("SSTL135")), - Subsignal("dm", Pins("W16 AD18 AE15 AB15 AD1 AC3 Y3 V6"), - IOStandard("SSTL135")), - Subsignal("dq", Pins( - "V19 V16 Y17 V14 V17 V18 W14 W15", - "AB17 AB19 AC18 AC19 AA19 AA20 AC17 AD19", - "AD16 AD15 AF20 AE17 AF17 AF19 AF14 AF15", - "AB16 AA15 AA14 AC14 AA18 AA17 AD14 AB14", - "AE3 AE6 AE2 AF3 AD4 AE5 AE1 AF2", - "AB6 Y6 AB4 AC4 AC6 AD6 Y5 AA4", - "AB2 AC2 V1 W1 V2 AA3 Y1 Y2", - "V4 V3 U2 U1 U7 W3 U6 U5"), - IOStandard("SSTL135_T_DCI")), - Subsignal("dqs_p", Pins("W18 AD20 AE18 Y15 AF5 AA5 AB1 W6"), - IOStandard("DIFF_SSTL135_T_DCI")), - Subsignal("dqs_n", Pins("W19 AE20 AF18 Y16 AF4 AB5 AC1 W5"), - IOStandard("DIFF_SSTL135_T_DCI")), - Subsignal("clk_p", Pins("V11 V8"), IOStandard("DIFF_SSTL135")), - Subsignal("clk_n", Pins("W11 V7"), IOStandard("DIFF_SSTL135")), - Subsignal("cke", Pins("AA10 AB10"), IOStandard("SSTL135")), - Subsignal("odt", Pins("AD13 Y13"), IOStandard("SSTL135")), - Subsignal("reset_n", Pins("AA2"), IOStandard("SSTL135")), - Misc("SLEW=FAST"), - ), - - ("spiflash4x", 0, # clock needs to be accessed through STARTUPE2 - Subsignal("cs_n", Pins("C23")), - Subsignal("dq", Pins("B24", "A25", "B22", "A22")), - IOStandard("LVCMOS33") - ), - + # SPIFlash ("spiflash", 0, # clock needs to be accessed through STARTUPE2 Subsignal("cs_n", Pins("C23")), Subsignal("mosi", Pins("B24")), @@ -131,14 +94,21 @@ _io = [ Subsignal("hold", Pins("A22")), IOStandard("LVCMOS33"), ), + ("spiflash4x", 0, # clock needs to be accessed through STARTUPE2 + Subsignal("cs_n", Pins("C23")), + Subsignal("dq", Pins("B24", "A25", "B22", "A22")), + IOStandard("LVCMOS33") + ), - ("mmc", 0, + # SDCard + ("sdcard", 0, Subsignal("cmd", Pins("H24")), Subsignal("clk", Pins("G22")), Subsignal("dat", Pins("F25 E25 J23 H23")), IOStandard("LVCMOS33") ), + # PCIe ("pcie_x1", 0, Subsignal("rst_n", Pins("E21"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")), Subsignal("clk_p", Pins("K6")), diff --git a/litex_boards/platforms/netv2.py b/litex_boards/platforms/netv2.py index 1c6d70e..8b27be4 100644 --- a/litex_boards/platforms/netv2.py +++ b/litex_boards/platforms/netv2.py @@ -11,10 +11,10 @@ from litex.build.openocd import OpenOCD # IOs ---------------------------------------------------------------------------------------------- _io = [ - # clock + # Clk / Rst ("clk50", 0, Pins("J19"), IOStandard("LVCMOS33")), - # leds + # Leds ("user_led", 0, Pins("M21"), IOStandard("LVCMOS33")), ("user_led", 1, Pins("N20"), IOStandard("LVCMOS33")), ("user_led", 2, Pins("L21"), IOStandard("LVCMOS33")), @@ -22,8 +22,8 @@ _io = [ ("user_led", 4, Pins("R19"), IOStandard("LVCMOS33")), ("user_led", 5, Pins("M16"), IOStandard("LVCMOS33")), - # spiflash - ("flash", 0, + # SPIFlash + ("spiflash", 0, Subsignal("cs_n", Pins("T19")), Subsignal("mosi", Pins("P22")), Subsignal("miso", Pins("R22")), @@ -31,22 +31,20 @@ _io = [ Subsignal("hold", Pins("R21")), IOStandard("LVCMOS33") ), - - # spiflash4x ("spiflash4x", 0, Subsignal("cs_n", Pins("T19")), Subsignal("dq", Pins("P22 R22 P21 R21")), IOStandard("LVCMOS33") ), - # serial + # Serial ("serial", 0, Subsignal("tx", Pins("E14")), Subsignal("rx", Pins("E13")), IOStandard("LVCMOS33"), ), - # dram + # DDR3 SDRAM ("ddram", 0, Subsignal("a", Pins( "U6 V4 W5 V5 AA1 Y2 AB1 AB3", @@ -75,7 +73,7 @@ _io = [ Misc("SLEW=FAST"), ), - # pcie + # PCIe ("pcie_x1", 0, Subsignal("rst_n", Pins("E18"), IOStandard("LVCMOS33")), Subsignal("clk_p", Pins("F10")), @@ -85,7 +83,6 @@ _io = [ Subsignal("tx_p", Pins("D5")), Subsignal("tx_n", Pins("C5")) ), - ("pcie_x2", 0, Subsignal("rst_n", Pins("E18"), IOStandard("LVCMOS33")), Subsignal("clk_p", Pins("F10")), @@ -95,7 +92,6 @@ _io = [ Subsignal("tx_p", Pins("D5 B6")), Subsignal("tx_n", Pins("C5 A6")) ), - ("pcie_x4", 0, Subsignal("rst_n", Pins("E18"), IOStandard("LVCMOS33")), Subsignal("clk_p", Pins("F10")), @@ -106,12 +102,11 @@ _io = [ Subsignal("tx_n", Pins("C5 A6 C7 A4")) ), - # ethernet + # RMII Ethernet ("eth_clocks", 0, Subsignal("ref_clk", Pins("D17")), IOStandard("LVCMOS33"), ), - ("eth", 0, Subsignal("rst_n", Pins("F16")), Subsignal("rx_data", Pins("A20 B18")), @@ -125,14 +120,7 @@ _io = [ IOStandard("LVCMOS33") ), - # sdcard - ("sdcard", 0, - Subsignal("clk", Pins("K18")), - Subsignal("cmd", Pins("L13"), Misc("PULLUP True")), - Subsignal("data", Pins("L15 L16 K14 M13"), Misc("PULLUP True")), - IOStandard("LVCMOS33"), Misc("SLEW=FAST") - ), - + # SDCard ("spisdcard", 0, Subsignal("clk", Pins("K18")), Subsignal("cs_n", Pins("M13")), @@ -141,8 +129,14 @@ _io = [ Misc("SLEW=FAST"), IOStandard("LVCMOS33") ), + ("sdcard", 0, + Subsignal("clk", Pins("K18")), + Subsignal("cmd", Pins("L13"), Misc("PULLUP True")), + Subsignal("data", Pins("L15 L16 K14 M13"), Misc("PULLUP True")), + IOStandard("LVCMOS33"), Misc("SLEW=FAST") + ), - # hdmi in + # HDMI In ("hdmi_in", 0, Subsignal("clk_p", Pins("L19"), IOStandard("TMDS_33"), Inverted()), Subsignal("clk_n", Pins("L20"), IOStandard("TMDS_33"), Inverted()), @@ -155,7 +149,6 @@ _io = [ Subsignal("scl", Pins("T18"), IOStandard("LVCMOS33")), Subsignal("sda", Pins("V18"), IOStandard("LVCMOS33")), ), - ("hdmi_in", 1, Subsignal("clk_p", Pins("Y18"), IOStandard("TMDS_33"), Inverted()), Subsignal("clk_n", Pins("Y19"), IOStandard("TMDS_33"), Inverted()), @@ -169,7 +162,7 @@ _io = [ Subsignal("sda", Pins("R17"), IOStandard("LVCMOS33")), ), - # hdmi out + # HDMI Out ("hdmi_out", 0, Subsignal("clk_p", Pins("W19"), IOStandard("TMDS_33"), Inverted()), Subsignal("clk_n", Pins("W20"), IOStandard("TMDS_33"), Inverted()), @@ -180,7 +173,6 @@ _io = [ Subsignal("data2_p", Pins("T21"), IOStandard("TMDS_33")), Subsignal("data2_n", Pins("U21"), IOStandard("TMDS_33")) ), - ("hdmi_out", 1, Subsignal("clk_p", Pins("G21"), IOStandard("TMDS_33"), Inverted()), Subsignal("clk_n", Pins("G22"), IOStandard("TMDS_33"), Inverted()), diff --git a/litex_boards/platforms/nexys4ddr.py b/litex_boards/platforms/nexys4ddr.py index 37dcf7a..76e79d7 100644 --- a/litex_boards/platforms/nexys4ddr.py +++ b/litex_boards/platforms/nexys4ddr.py @@ -11,6 +11,11 @@ from litex.build.openocd import OpenOCD # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst + ("clk100", 0, Pins("E3"), IOStandard("LVCMOS33")), + ("cpu_reset", 0, Pins("C12"), IOStandard("LVCMOS33")), + + # Leds ("user_led", 0, Pins("H17"), IOStandard("LVCMOS33")), ("user_led", 1, Pins("K15"), IOStandard("LVCMOS33")), ("user_led", 2, Pins("J13"), IOStandard("LVCMOS33")), @@ -28,6 +33,7 @@ _io = [ ("user_led", 14, Pins("V12"), IOStandard("LVCMOS33")), ("user_led", 15, Pins("V11"), IOStandard("LVCMOS33")), + # Switches ("user_sw", 0, Pins("J15"), IOStandard("LVCMOS33")), ("user_sw", 1, Pins("L16"), IOStandard("LVCMOS33")), ("user_sw", 2, Pins("M13"), IOStandard("LVCMOS33")), @@ -45,22 +51,21 @@ _io = [ ("user_sw", 14, Pins("U11"), IOStandard("LVCMOS33")), ("user_sw", 15, Pins("V10"), IOStandard("LVCMOS33")), + # Buttons ("user_btn", 0, Pins("N17"), IOStandard("LVCMOS33")), ("user_btn", 1, Pins("P18"), IOStandard("LVCMOS33")), ("user_btn", 2, Pins("P17"), IOStandard("LVCMOS33")), ("user_btn", 3, Pins("M17"), IOStandard("LVCMOS33")), ("user_btn", 4, Pins("M18"), IOStandard("LVCMOS33")), - ("clk100", 0, Pins("E3"), IOStandard("LVCMOS33")), - - ("cpu_reset", 0, Pins("C12"), IOStandard("LVCMOS33")), - + # Serial ("serial", 0, Subsignal("tx", Pins("D4")), Subsignal("rx", Pins("C4")), IOStandard("LVCMOS33"), ), + # SDCard ("spisdcard", 0, Subsignal("rst", Pins("E2")), Subsignal("clk", Pins("B1")), @@ -70,7 +75,6 @@ _io = [ Misc("SLEW=FAST"), IOStandard("LVCMOS33"), ), - ("sdcard", 0, Subsignal("rst", Pins("E2"), Misc("PULLUP True")), Subsignal("data", Pins("C2 E1 F1 D2"), Misc("PULLUP True")), @@ -81,6 +85,7 @@ _io = [ IOStandard("LVCMOS33"), ), + # DDR2 SDRAM ("ddram", 0, Subsignal("a", Pins( "M4 P4 M6 T1 L3 P5 M2 N1", @@ -106,6 +111,7 @@ _io = [ Misc("SLEW=FAST"), ), + # RMII Ethernet ("eth_clocks", 0, Subsignal("ref_clk", Pins("D5")), IOStandard("LVCMOS33"), diff --git a/litex_boards/platforms/nexys_video.py b/litex_boards/platforms/nexys_video.py index fe65d4c..c098694 100644 --- a/litex_boards/platforms/nexys_video.py +++ b/litex_boards/platforms/nexys_video.py @@ -11,10 +11,11 @@ from litex.build.openocd import OpenOCD # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst ("clk100", 0, Pins("R4"), IOStandard("LVCMOS33")), - ("cpu_reset", 0, Pins("G4"), IOStandard("LVCMOS15")), + # Leds ("user_led", 0, Pins("T14"), IOStandard("LVCMOS25")), ("user_led", 1, Pins("T15"), IOStandard("LVCMOS25")), ("user_led", 2, Pins("T16"), IOStandard("LVCMOS25")), @@ -24,6 +25,7 @@ _io = [ ("user_led", 6, Pins("W15"), IOStandard("LVCMOS25")), ("user_led", 7, Pins("Y13"), IOStandard("LVCMOS25")), + # Switches ("user_sw", 0, Pins("E22"), IOStandard("LVCMOS25")), ("user_sw", 1, Pins("F21"), IOStandard("LVCMOS25")), ("user_sw", 2, Pins("G21"), IOStandard("LVCMOS25")), @@ -33,7 +35,7 @@ _io = [ ("user_sw", 6, Pins("K13"), IOStandard("LVCMOS25")), ("user_sw", 7, Pins("M17"), IOStandard("LVCMOS25")), - + # Buttons ("user_btn", 0, Pins("B22"), IOStandard("LVCMOS25")), ("user_btn", 1, Pins("D22"), IOStandard("LVCMOS25")), ("user_btn", 2, Pins("C22"), IOStandard("LVCMOS25")), @@ -41,8 +43,7 @@ _io = [ ("user_btn", 4, Pins("F15"), IOStandard("LVCMOS25")), ("user_btn", 5, Pins("G4"), IOStandard("LVCMOS25")), - ("vadj", 0, Pins("AA13 AB17"), IOStandard("LVCMOS25")), - + # OLED ("oled", 0, Subsignal("dc", Pins("W22")), Subsignal("res", Pins("U21")), @@ -53,12 +54,14 @@ _io = [ IOStandard("LVCMOS33") ), + # Serial ("serial", 0, Subsignal("tx", Pins("AA19")), Subsignal("rx", Pins("V18")), IOStandard("LVCMOS33"), ), + # USB FIFO ("usb_fifo", 0, # Can be used when FT2232H's Channel A configured to ASYNC FIFO 245 mode Subsignal("data", Pins("U20 P14 P15 U17 R17 P16 R18 N14")), Subsignal("rxf_n", Pins("N17")), @@ -72,6 +75,7 @@ _io = [ IOStandard("LVCMOS33"), ), + # SDCard ("spisdcard", 0, Subsignal("rst", Pins("V20")), Subsignal("clk", Pins("W19")), @@ -91,6 +95,7 @@ _io = [ IOStandard("LVCMOS33"), ), + # DDR3 SDRAM ("ddram", 0, Subsignal("a", Pins( "M2 M5 M3 M1 L6 P1 N3 N2", @@ -116,6 +121,7 @@ _io = [ Misc("SLEW=FAST"), ), + # MII Ethernet ("eth_clocks", 0, Subsignal("tx", Pins("AA14")), Subsignal("rx", Pins("V13")), @@ -133,6 +139,7 @@ _io = [ IOStandard("LVCMOS25") ), + # HDMI In ("hdmi_in", 0, Subsignal("clk_p", Pins("V4"), IOStandard("TMDS_33")), Subsignal("clk_n", Pins("W4"), IOStandard("TMDS_33")), @@ -149,6 +156,7 @@ _io = [ Subsignal("txen", Pins("R3"), IOStandard("LVCMOS33")), # FIXME ), + # HDMI Out ("hdmi_out", 0, Subsignal("clk_p", Pins("T1"), IOStandard("TMDS_33")), Subsignal("clk_n", Pins("U1"), IOStandard("TMDS_33")), @@ -163,6 +171,9 @@ _io = [ Subsignal("cec", Pins("AA4"), IOStandard("LVCMOS33")), # FIXME Subsignal("hdp", Pins("AB13"), IOStandard("LVCMOS25")), # FIXME ), + + # Others + ("vadj", 0, Pins("AA13 AB17"), IOStandard("LVCMOS25")), ] # Connectors --------------------------------------------------------------------------------------- diff --git a/litex_boards/platforms/orangecrab.py b/litex_boards/platforms/orangecrab.py index 4b048fe..03a4a46 100644 --- a/litex_boards/platforms/orangecrab.py +++ b/litex_boards/platforms/orangecrab.py @@ -11,19 +11,21 @@ from litex.build.dfu import DFUProg # IOs ---------------------------------------------------------------------------------------------- _io_r0_1 = [ + # Clk / Rst ("clk48", 0, Pins("A9"), IOStandard("LVCMOS33")), ("rst_n", 0, Pins("R16"), IOStandard("LVCMOS33")), + # Leds + ("user_led", 0, Pins("V17"), IOStandard("LVCMOS33")), # rgb_led.r + ("user_led", 1, Pins("T17"), IOStandard("LVCMOS33")), # rgb_led.g + ("user_led", 2, Pins("J3"), IOStandard("LVCMOS33")), # rgb_led.b ("rgb_led", 0, Subsignal("r", Pins("V17"), IOStandard("LVCMOS33")), Subsignal("g", Pins("T17"), IOStandard("LVCMOS33")), Subsignal("b", Pins("J3"), IOStandard("LVCMOS33")), ), - ("user_led", 0, Pins("V17"), IOStandard("LVCMOS33")), # rgb_led.r - ("user_led", 1, Pins("T17"), IOStandard("LVCMOS33")), # rgb_led.g - ("user_led", 2, Pins("J3"), IOStandard("LVCMOS33")), # rgb_led.b - + # DDR3 SDRAM ("ddram", 0, Subsignal("a", Pins( "A4 D2 C3 C7 D3 D4 D1 B2", @@ -49,6 +51,7 @@ _io_r0_1 = [ Misc("SLEWRATE=FAST") ), + # USB ("usb", 0, Subsignal("d_p", Pins("N1")), Subsignal("d_n", Pins("M2")), @@ -56,13 +59,15 @@ _io_r0_1 = [ IOStandard("LVCMOS33") ), + # SPIFlash ("spiflash4x", 0, Subsignal("cs_n", Pins("U17")), - # Subsignal("clk", Pins("U16")), + #Subsignal("clk", Pins("U16")), Subsignal("dq", Pins("U18 T18 R18 N18")), IOStandard("LVCMOS33") ), + # SPI ("spi-internal", 0, Subsignal("cs_n", Pins("B11"), Misc("PULLMODE=UP")), Subsignal("clk", Pins("C11")), @@ -72,6 +77,7 @@ _io_r0_1 = [ IOStandard("LVCMOS33"), ), + # SDCard ("spisdcard", 0, Subsignal("clk", Pins("K1")), Subsignal("mosi", Pins("K2"), Misc("PULLMODE=UP")), @@ -83,21 +89,24 @@ _io_r0_1 = [ ] _io_r0_2 = [ + # Clk / Rst ("clk48", 0, Pins("A9"), IOStandard("LVCMOS33")), ("rst_n", 0, Pins("V17"), IOStandard("LVCMOS33")), + # Buttons ("usr_btn", 0, Pins("J17"), IOStandard("SSTL135_I")), + # Leds + ("user_led", 0, Pins("K4"), IOStandard("LVCMOS33")), # rgb_led.r + ("user_led", 1, Pins("M3"), IOStandard("LVCMOS33")), # rgb_led.g + ("user_led", 2, Pins("J3"), IOStandard("LVCMOS33")), # rgb_led.b ("rgb_led", 0, Subsignal("r", Pins("K4"), IOStandard("LVCMOS33")), Subsignal("g", Pins("M3"), IOStandard("LVCMOS33")), Subsignal("b", Pins("J3"), IOStandard("LVCMOS33")), ), - ("user_led", 0, Pins("K4"), IOStandard("LVCMOS33")), # rgb_led.r - ("user_led", 1, Pins("M3"), IOStandard("LVCMOS33")), # rgb_led.g - ("user_led", 2, Pins("J3"), IOStandard("LVCMOS33")), # rgb_led.b - + # DDR3 SDRAM ("ddram", 0, Subsignal("a", Pins( "C4 D2 D3 A3 A4 D4 C3 B2", @@ -126,6 +135,7 @@ _io_r0_2 = [ Misc("SLEWRATE=FAST") ), + # USB ("usb", 0, Subsignal("d_p", Pins("N1")), Subsignal("d_n", Pins("M2")), @@ -133,6 +143,7 @@ _io_r0_2 = [ IOStandard("LVCMOS33") ), + # SPIFlash ("spiflash4x", 0, Subsignal("cs_n", Pins("U17"), IOStandard("LVCMOS33")), #Subsignal("clk", Pins("U16"), IOStandard("LVCMOS33")), @@ -147,6 +158,7 @@ _io_r0_2 = [ Subsignal("hold", Pins("N18"), IOStandard("LVCMOS33")), ), + # SDCard ("spisdcard", 0, Subsignal("clk", Pins("K1")), Subsignal("mosi", Pins("K2"), Misc("PULLMODE=UP")), @@ -202,7 +214,6 @@ feather_spi = [ ) ] - # Platform ----------------------------------------------------------------------------------------- class Platform(LatticePlatform): diff --git a/litex_boards/platforms/pano_logic_g2.py b/litex_boards/platforms/pano_logic_g2.py index 824cc33..3e46750 100644 --- a/litex_boards/platforms/pano_logic_g2.py +++ b/litex_boards/platforms/pano_logic_g2.py @@ -17,33 +17,33 @@ from litex.build.openocd import OpenOCD # IOs ---------------------------------------------------------------------------------------------- _io = [ - # clock / reset + # Clk / Rst ("clk125", 0, Pins("Y13"), IOStandard("LVCMOS33")), ("rst_n", 0, Pins("AB14"), IOStandard("LVCMOS33")), - # led + # Leds ("user_led", 0, Pins("E12"), IOStandard("LVCMOS33")), ("user_led", 1, Pins("H13"), IOStandard("LVCMOS33")), ("user_led", 2, Pins("F13"), IOStandard("LVCMOS33")), - # btn + # Buttons ("user_btn_n", 0, Pins("H12"), IOStandard("LVCMOS33")), - # serial + # Serial ("serial", 0, # hdmi Subsignal("tx", Pins("AB19")), Subsignal("rx", Pins("AA21")), IOStandard("LVCMOS33") ), - # serial + # Serial ("serial", 1, # dvi Subsignal("tx", Pins("C14")), Subsignal("rx", Pins("C17")), IOStandard("LVCMOS33") ), - # spi flash + # SPIFlash ("spiflash", 0, Subsignal("cs_n", Pins("T5"), IOStandard("LVCMOS33")), Subsignal("clk", Pins("Y21"), IOStandard("LVCMOS33")), @@ -51,7 +51,7 @@ _io = [ Subsignal("miso", Pins("AA20"), IOStandard("LVCMOS33")) ), - # ddram + # DDR2 SDRAM ("ddram_clock_a", 0, Subsignal("p", Pins("H20")), Subsignal("n", Pins("J19")), @@ -76,7 +76,6 @@ _io = [ Subsignal("cke", Pins("D21"), IOStandard("SSTL18_II")), Subsignal("odt", Pins("G22"), IOStandard("SSTL18_II")), ), - ("ddram_clock_b", 0, Subsignal("p", Pins("H4")), Subsignal("n", Pins("H3")), @@ -102,7 +101,7 @@ _io = [ Subsignal("odt", Pins("J6"), IOStandard("SSTL18_II")), ), - # ethernet + # GMII Ethernet ("eth_rst_n", 0, Pins("R11"), IOStandard("LVCMOS33")), ("eth_clocks", 0, Subsignal("tx", Pins("Y11")), @@ -125,7 +124,6 @@ _io = [ Subsignal("crs", Pins("W4")), IOStandard("LVCMOS33") ), - ] # Platform ----------------------------------------------------------------------------------------- diff --git a/litex_boards/platforms/pipistrello.py b/litex_boards/platforms/pipistrello.py index b98630a..8c41665 100644 --- a/litex_boards/platforms/pipistrello.py +++ b/litex_boards/platforms/pipistrello.py @@ -15,16 +15,20 @@ from litex.build.xilinx.programmer import XC3SProg # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst ("clk50", 0, Pins("H17"), IOStandard("LVTTL")), - ("user_btn", 0, Pins("N14"), IOStandard("LVTTL"), Misc("PULLDOWN")), + # Leds + ("user_led", 0, Pins("V16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # Green at hdmi + ("user_led", 1, Pins("U16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # Red at hdmi + ("user_led", 2, Pins("A16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # Green at msd + ("user_led", 3, Pins("A15"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # Red at msd + ("user_led", 4, Pins("A12"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # Red at usb - ("user_led", 0, Pins("V16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # green at hdmi - ("user_led", 1, Pins("U16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at hdmi - ("user_led", 2, Pins("A16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # green at msd - ("user_led", 3, Pins("A15"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at msd - ("user_led", 4, Pins("A12"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at usb + # Buttons + ("user_btn", 0, Pins("N14"), IOStandard("LVTTL"), Misc("PULLDOWN")), + # Serial ("serial", 0, Subsignal("tx", Pins("A10")), Subsignal("rx", Pins("A11"), Misc("PULLUP")), @@ -33,6 +37,7 @@ _io = [ IOStandard("LVTTL"), ), + # USB FIFO ("usb_fifo", 0, Subsignal("data", Pins("A11 A10 C10 A9 B9 A8 B8 A7")), Subsignal("rxf_n", Pins("C7")), @@ -43,6 +48,7 @@ _io = [ IOStandard("LVTTL"), ), + # HDMI ("hdmi", 0, Subsignal("clk_p", Pins("U5"), IOStandard("TMDS_33")), Subsignal("clk_n", Pins("V5"), IOStandard("TMDS_33")), @@ -57,6 +63,7 @@ _io = [ Subsignal("hpd_notif", Pins("R8"), IOStandard("LVTTL")), ), + # SPIFlash ("spiflash", 0, Subsignal("cs_n", Pins("V3")), Subsignal("clk", Pins("R15")), @@ -67,7 +74,6 @@ _io = [ Misc("SLEW=FAST"), IOStandard("LVTTL") ), - ("spiflash2x", 0, Subsignal("cs_n", Pins("V3")), Subsignal("clk", Pins("R15")), @@ -77,7 +83,6 @@ _io = [ Misc("SLEW=FAST"), IOStandard("LVTTL"), ), - ("spiflash4x", 0, Subsignal("cs_n", Pins("V3")), Subsignal("clk", Pins("R15")), @@ -86,38 +91,34 @@ _io = [ IOStandard("LVTTL"), ), - ("mmc", 0, - Subsignal("clk", Pins("A3")), - Subsignal("cmd", Pins("B3"), Misc("PULLUP")), - Subsignal("dat", Pins("B4 A4 B2 A2"), Misc("PULLUP")), - IOStandard("SDIO") - ), - - ("mmc_spi", 0, + # SDCard + ("spisdcard", 0, Subsignal("cs_n", Pins("A2"), Misc("PULLUP")), Subsignal("clk", Pins("A3")), Subsignal("mosi", Pins("B3")), Subsignal("miso", Pins("B4"), Misc("PULLUP")), IOStandard("SDIO") ), + ("sdcard", 0, + Subsignal("clk", Pins("A3")), + Subsignal("cmd", Pins("B3"), Misc("PULLUP")), + Subsignal("dat", Pins("B4 A4 B2 A2"), Misc("PULLUP")), + IOStandard("SDIO") + ), + # Audio ("audio", 0, Subsignal("l", Pins("R7"), Misc("SLEW=SLOW")), Subsignal("r", Pins("T7"), Misc("SLEW=SLOW")), IOStandard("LVTTL"), ), - ("pmod", 0, - Subsignal("d", Pins("D9 C8 D6 C4 B11 C9 D8 C6")), - IOStandard("LVTTL") - ), - + # LPDDR SDRAM ("ddram_clock", 0, Subsignal("p", Pins("G3")), Subsignal("n", Pins("G1")), IOStandard("MOBILE_DDR") ), - ("ddram", 0, Subsignal("a", Pins( "J7 J6 H5 L7 F3 H4 H3 H6", @@ -133,7 +134,13 @@ _io = [ Subsignal("dqs", Pins("L4 P2")), Subsignal("dm", Pins("K3 K4")), IOStandard("MOBILE_DDR") - ) + ), + + # PMOD + ("pmod", 0, + Subsignal("d", Pins("D9 C8 D6 C4 B11 C9 D8 C6")), + IOStandard("LVTTL") + ), ] # Connectors --------------------------------------------------------------------------------------- diff --git a/litex_boards/platforms/sp605.py b/litex_boards/platforms/sp605.py index 80d8387..c274832 100644 --- a/litex_boards/platforms/sp605.py +++ b/litex_boards/platforms/sp605.py @@ -11,18 +11,28 @@ from litex.build.openocd import OpenOCD # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst + ("clk200", 0, + Subsignal("p", Pins("K21")), + Subsignal("n", Pins("K22")), + IOStandard("LVDS_25") + ), + ("cpu_reset", 0, Pins("H8"), IOStandard("LVCMOS25")), + + # Leds ("user_led", 0, Pins("D17"), IOStandard("LVCMOS25")), ("user_led", 1, Pins("AB4"), IOStandard("LVCMOS25")), ("user_led", 2, Pins("D21"), IOStandard("LVCMOS25")), ("user_led", 3, Pins("W15"), IOStandard("LVCMOS25")), + # Buttons ("user_btn", 0, Pins("F3"), IOStandard("LVCMOS25")), ("user_btn", 1, Pins("G6"), IOStandard("LVCMOS25")), ("user_btn", 2, Pins("F5"), IOStandard("LVCMOS25")), ("user_btn", 3, Pins("C1"), IOStandard("LVCMOS25")), - ("cpu_reset", 0, Pins("H8"), IOStandard("LVCMOS25")), + # Serial ("serial", 0, Subsignal("cts", Pins("F19")), Subsignal("rts", Pins("F18")), @@ -31,12 +41,7 @@ _io = [ IOStandard("LVCMOS25") ), - ("clk200", 0, - Subsignal("p", Pins("K21")), - Subsignal("n", Pins("K22")), - IOStandard("LVDS_25") - ), - + # GMII Ethernet ("eth_clocks", 0, # Subsignal("tx", Pins("L20")), # Comment to force GMII 1G only mode Subsignal("gtx", Pins("AB7")), diff --git a/litex_boards/platforms/tagus.py b/litex_boards/platforms/tagus.py index f7c565b..ce6ad8a 100644 --- a/litex_boards/platforms/tagus.py +++ b/litex_boards/platforms/tagus.py @@ -12,15 +12,14 @@ from litex.build.openocd import OpenOCD # IOs ---------------------------------------------------------------------------------------------- _io = [ - # clk / rst + # Clk / Rst ("clk100", 0, Pins("W19"), IOStandard("LVCMOS33")), ("rst", 0, Pins("P17"), IOStandard("LVCMOS33")), - # leds (only a single rgb led, aliased here also) + # Leds (only a single rgb led, aliased here also) ("user_led", 0, Pins("W21"), IOStandard("LVCMOS33")), ("user_led", 1, Pins("W22"), IOStandard("LVCMOS33")), ("user_led", 2, Pins("AA20"), IOStandard("LVCMOS33")), - ("rgb_led", 0, Subsignal("r", Pins("W21")), Subsignal("g", Pins("W22")), @@ -28,17 +27,18 @@ _io = [ IOStandard("LVCMOS33"), ), + # Serial ("serial", 0, - Subsignal("tx", Pins("R14")), - Subsignal("rx", Pins("P14")), - Subsignal("rts", Pins("R18")), - Subsignal("cts", Pins("T18")), - Subsignal("cbus0", Pins("N17")), - IOStandard("LVCMOS33") + Subsignal("tx", Pins("R14")), + Subsignal("rx", Pins("P14")), + Subsignal("rts", Pins("R18")), + Subsignal("cts", Pins("T18")), + Subsignal("cbus0", Pins("N17")), + IOStandard("LVCMOS33") ), - # flash - ("flash", 0, + # SPIFlash + ("spiflash", 0, Subsignal("cs_n", Pins("T19")), Subsignal("mosi", Pins("P22")), Subsignal("miso", Pins("R22")), @@ -46,14 +46,13 @@ _io = [ Subsignal("hold", Pins("R21")), IOStandard("LVCMOS33") ), - - ("flash4x", 0, # clock needs to be accessed through STARTUPE2 + ("spiflash4x", 0, # clock needs to be accessed through STARTUPE2 Subsignal("cs_n", Pins("T19")), Subsignal("dq", Pins("P22", "R22", "P21", "R21")), IOStandard("LVCMOS33") ), - # tpm + # TPM ("tpm", 0, Subsignal("clk", Pins("Y18")), Subsignal("rst_n", Pins("AA19")), @@ -63,7 +62,7 @@ _io = [ IOStandard("LVCMOS33"), ), - # pcie + # PCIe ("pcie_x1", 0, Subsignal("rst_n", Pins("W20"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")), Subsignal("clk_p", Pins("F6")), @@ -74,7 +73,7 @@ _io = [ Subsignal("tx_n", Pins("A4")) ), - # dram + # DDR3 SDRAM ("ddram", 0, Subsignal("a", Pins( "U6 T5 Y6 T6 V2 T4 Y2 R2", @@ -101,7 +100,7 @@ _io = [ Misc("SLEW=FAST"), ), - # sdcard + # SDCard ("sdcard", 0, Subsignal("data", Pins("P19 Y22 Y21 T21")), Subsignal("cmd", Pins("U21")), @@ -110,7 +109,7 @@ _io = [ IOStandard("LVCMOS33"), ), - # sfp0 + # SFP0 ("sfp_tx", 0, Subsignal("p", Pins("B6")), Subsignal("n", Pins("A6")) @@ -122,7 +121,7 @@ _io = [ ("sfp_tx_disable_n", 0, Pins("V22"), IOStandard("LVCMOS33")), ("sfp_rx_los", 0, Pins("AB21"), IOStandard("LVCMOS33")), - # sfp1 + # SFP1 ("sfp_tx", 1, Subsignal("p", Pins("D7")), Subsignal("n", Pins("C7")), diff --git a/litex_boards/platforms/tec0117.py b/litex_boards/platforms/tec0117.py index 701ca9c..6398928 100644 --- a/litex_boards/platforms/tec0117.py +++ b/litex_boards/platforms/tec0117.py @@ -9,10 +9,11 @@ from litex.build.openfpgaloader import OpenFPGALoader # IOs ---------------------------------------------------------------------------------------------- _io = [ - ("user_led", 0, Pins("86"), IOStandard("LVCMOS33")), + # Clk / Rst ("clk12", 0, Pins("35"), IOStandard("LVCMOS33")), ("rst", 0, Pins("77"), IOStandard("LVCMOS33")), + # Leds ("user_led", 0, Pins("86"), IOStandard("LVCMOS33")), ("user_led", 1, Pins("85"), IOStandard("LVCMOS33")), ("user_led", 2, Pins("84"), IOStandard("LVCMOS33")), @@ -22,11 +23,13 @@ _io = [ ("user_led", 6, Pins("80"), IOStandard("LVCMOS33")), ("user_led", 7, Pins("79"), IOStandard("LVCMOS33")), + # Serial ("serial", 0, Subsignal("tx", Pins("15"), IOStandard("LVCMOS33")), Subsignal("rx", Pins("16"), IOStandard("LVCMOS33")) ), + # SPIFlash ("spiflash", 0, Subsignal("cs_n", Pins("51"), IOStandard("LVCMOS33")), Subsignal("clk", Pins("49"), IOStandard("LVCMOS33")), @@ -36,14 +39,13 @@ _io = [ Subsignal("hold", Pins("50"), IOStandard("LVCMOS33")), ), - # this one is the FTDI chip + # SPIFlash (FTDI Chip) ("spiflash", 1, Subsignal("cs_n", Pins("13"), IOStandard("LVCMOS33")), Subsignal("clk", Pins("16"), IOStandard("LVCMOS33")), Subsignal("miso", Pins("14"), IOStandard("LVCMOS33")), Subsignal("mosi", Pins("15"), IOStandard("LVCMOS33")), ), - ] # Connectors --------------------------------------------------------------------------------------- @@ -63,4 +65,3 @@ class Platform(GowinPlatform): def create_programmer(self): return OpenFPGALoader("littlebee") - diff --git a/litex_boards/platforms/tinyfpga_bx.py b/litex_boards/platforms/tinyfpga_bx.py index b722819..347cd86 100644 --- a/litex_boards/platforms/tinyfpga_bx.py +++ b/litex_boards/platforms/tinyfpga_bx.py @@ -12,8 +12,13 @@ from litex.build.lattice.programmer import TinyProgProgrammer # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst + ("clk16", 0, Pins("B2"), IOStandard("LVCMOS33")), + + # Leds ("user_led", 0, Pins("B3"), IOStandard("LVCMOS33")), + # USB ("usb", 0, Subsignal("d_p", Pins("B4")), Subsignal("d_n", Pins("A4")), @@ -21,6 +26,7 @@ _io = [ IOStandard("LVCMOS33") ), + # SPIFlash ("spiflash", 0, Subsignal("cs_n", Pins("F7"), IOStandard("LVCMOS33")), Subsignal("clk", Pins("G7"), IOStandard("LVCMOS33")), @@ -29,14 +35,11 @@ _io = [ Subsignal("wp", Pins("H4"), IOStandard("LVCMOS33")), Subsignal("hold", Pins("J8"), IOStandard("LVCMOS33")) ), - ("spiflash4x", 0, Subsignal("cs_n", Pins("F7"), IOStandard("LVCMOS33")), Subsignal("clk", Pins("G7"), IOStandard("LVCMOS33")), Subsignal("dq", Pins("G6 H7 H4 J8"), IOStandard("LVCMOS33")) ), - - ("clk16", 0, Pins("B2"), IOStandard("LVCMOS33")) ] # Connectors --------------------------------------------------------------------------------------- diff --git a/litex_boards/platforms/trellisboard.py b/litex_boards/platforms/trellisboard.py index 04663a7..fd35511 100644 --- a/litex_boards/platforms/trellisboard.py +++ b/litex_boards/platforms/trellisboard.py @@ -11,15 +11,32 @@ from litex.build.lattice.programmer import OpenOCDJTAGProgrammer # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst ("clk100", 0, Pins("B29"), IOStandard("LVDS")), # [broken on rev1.0 (non diff pair)] ("clk12", 0, Pins("B3"), IOStandard("LVCMOS33")), ("clkref", 0, Pins("E17"), IOStandard("LVCMOS33")), + # Leds + ("user_led", 0, Pins("C26"), IOStandard("LVCMOS33"), Misc("PULLMODE=NONE")), + ("user_led", 1, Pins("D26"), IOStandard("LVCMOS33"), Misc("PULLMODE=NONE")), + ("user_led", 2, Pins("A28"), IOStandard("LVCMOS33"), Misc("PULLMODE=NONE")), + ("user_led", 3, Pins("A29"), IOStandard("LVCMOS33"), Misc("PULLMODE=NONE")), + ("user_led", 4, Pins("A30"), IOStandard("LVCMOS33"), Misc("PULLMODE=NONE")), + ("user_led", 5, Pins("AK29"), IOStandard("LVCMOS33"), Misc("PULLMODE=NONE")), + ("user_led", 6, Pins("AH32"), IOStandard("LVCMOS33"), Misc("PULLMODE=NONE")), + ("user_led", 7, Pins("AH30"), IOStandard("LVCMOS33"), Misc("PULLMODE=NONE")), + ("user_led", 8, Pins("AH28"), IOStandard("LVCMOS33"), Misc("PULLMODE=NONE")), + ("user_led", 9, Pins("AG30"), IOStandard("LVCMOS33"), Misc("PULLMODE=NONE")), + ("user_led", 10, Pins("AG29"), IOStandard("LVCMOS33"), Misc("PULLMODE=NONE")), + ("user_led", 11, Pins("AK30"), IOStandard("LVCMOS33"), Misc("PULLMODE=NONE")), + + # Buttons ("user_btn", 0, Pins("Y32"), IOStandard("SSTL135_I")), ("user_btn", 1, Pins("W31"), IOStandard("SSTL135_I")), ("user_btn", 2, Pins("AD30"), IOStandard("SSTL135_I")), ("user_btn", 3, Pins("AD29"), IOStandard("SSTL135_I")), + # Switches ("user_dip", 0, Pins("AE31"), IOStandard("SSTL135_I")), ("user_dip", 1, Pins("AE32"), IOStandard("SSTL135_I")), ("user_dip", 2, Pins("AD32"), IOStandard("SSTL135_I")), @@ -29,25 +46,14 @@ _io = [ ("user_dip", 6, Pins("AC31"), IOStandard("SSTL135_I")), ("user_dip", 7, Pins("AC30"), IOStandard("SSTL135_I")), - ("user_led", 0, Pins("C26"), IOStandard("LVCMOS33"), Misc("PULLMODE=NONE")), - ("user_led", 1, Pins("D26"), IOStandard("LVCMOS33"), Misc("PULLMODE=NONE")), - ("user_led", 2, Pins("A28"), IOStandard("LVCMOS33"), Misc("PULLMODE=NONE")), - ("user_led", 3, Pins("A29"), IOStandard("LVCMOS33"), Misc("PULLMODE=NONE")), - ("user_led", 4, Pins("A30"), IOStandard("LVCMOS33"), Misc("PULLMODE=NONE")), - ("user_led", 5, Pins("AK29"), IOStandard("LVCMOS33"), Misc("PULLMODE=NONE")), - ("user_led", 6, Pins("AH32"), IOStandard("LVCMOS33"), Misc("PULLMODE=NONE")), - ("user_led", 7, Pins("AH30"), IOStandard("LVCMOS33"), Misc("PULLMODE=NONE")), - ("user_led", 8, Pins("AH28"), IOStandard("LVCMOS33"), Misc("PULLMODE=NONE")), - ("user_led", 9, Pins("AG30"), IOStandard("LVCMOS33"), Misc("PULLMODE=NONE")), - ("user_led", 10, Pins("AG29"), IOStandard("LVCMOS33"), Misc("PULLMODE=NONE")), - ("user_led", 11, Pins("AK30"), IOStandard("LVCMOS33"), Misc("PULLMODE=NONE")), - + # Serial ("serial", 0, Subsignal("rx", Pins("AM28"), IOStandard("LVCMOS33")), Subsignal("tx", Pins("AL28"), IOStandard("LVCMOS33")), ), - ("ftdi", 0, + # USB FIFO + ("usb_fifo", 0, Subsignal("dq", Pins("AM28 AL28 AM29 AK28 AK32 AM30 AJ32 AL30"), IOStandard("LVCMOS33")), Subsignal("txe_n", Pins("AM31"), IOStandard("LVCMOS33")), Subsignal("rxf_n", Pins("AJ31"), IOStandard("LVCMOS33")), @@ -56,6 +62,7 @@ _io = [ Subsignal("siwu_n", Pins("AJ28"), IOStandard("LVCMOS33")), ), + # DDR3 SDRAM ("dram_vtt_en", 0, Pins("E25"), IOStandard("LVCMOS33")), ("ddram", 0, Subsignal("a", Pins( @@ -85,13 +92,13 @@ _io = [ Misc("SLEWRATE=FAST"), ), + # RGMII Ethernet ("eth_clocks", 0, Subsignal("tx", Pins("A15")), Subsignal("rx", Pins("C17")), Subsignal("ref", Pins("A17")), IOStandard("LVCMOS33") ), - ("eth", 0, Subsignal("rst_n", Pins("D16")), Subsignal("int_n", Pins("E16")), @@ -104,6 +111,7 @@ _io = [ IOStandard("LVCMOS33") ), + # I2C Clock Generator ("clkgen", 0, Subsignal("sda", Pins("C22")), Subsignal("scl", Pins("A22")), @@ -111,7 +119,7 @@ _io = [ IOStandard("LVCMOS33") ), - + # PCIe ("pcie_x2", 0, Subsignal("clk_p", Pins("AM14")), Subsignal("clk_n", Pins("AM15")), @@ -123,6 +131,7 @@ _io = [ Subsignal("wake_n", Pins("A23"), IOStandard("LVCMOS33")), ), + # M2 ("m2", 0, Subsignal("clk_p", Pins("AM23")), Subsignal("clk_n", Pins("AM24")), @@ -143,6 +152,7 @@ _io = [ Subsignal("uart_cts_n", Pins("P7"), IOStandard("LVCMOS33")) ), + # SDCard ("spisdcard", 0, Subsignal("clk", Pins("AK3")), Subsignal("mosi", Pins("AH3"), Misc("PULLMODE=UP")), @@ -151,7 +161,6 @@ _io = [ Misc("SLEWRATE=FAST"), IOStandard("LVCMOS33"), ), - ("sdcard", 0, Subsignal("clk", Pins("AK3")), Subsignal("cmd", Pins("AH3"), Misc("PULLMODE=UP")), @@ -160,13 +169,8 @@ _io = [ IOStandard("LVCMOS33"), ), - ("spiflash4x", 0, - Subsignal("clk", Pins("AM3")), - Subsignal("cs_n", Pins("AJ3")), - Subsignal("dq", Pins("AK2 AJ2 AM2 AL1")), - IOStandard("LVCMOS33") - ), + # SPIFlash ("spiflash", 0, Subsignal("clk", Pins("AM3")), Subsignal("cs_n", Pins("AJ3")), @@ -176,7 +180,14 @@ _io = [ Subsignal("hold", Pins("AL1")), IOStandard("LVCMOS33") ), + ("spiflash4x", 0, + Subsignal("clk", Pins("AM3")), + Subsignal("cs_n", Pins("AJ3")), + Subsignal("dq", Pins("AK2 AJ2 AM2 AL1")), + IOStandard("LVCMOS33") + ), + # USB ULPI ("ulpi", 0, Subsignal("clk", Pins("A18")), Subsignal("stp", Pins("D18")), @@ -187,6 +198,7 @@ _io = [ IOStandard("LVCMOS33") ), + # HDMI ("hdmi", 0, Subsignal("d", Pins( "C11 A11 B11 A10 B10 C10 A8 B7", diff --git a/litex_boards/platforms/ulx3s.py b/litex_boards/platforms/ulx3s.py index 4a1956a..f360259 100644 --- a/litex_boards/platforms/ulx3s.py +++ b/litex_boards/platforms/ulx3s.py @@ -11,9 +11,11 @@ from litex.build.lattice.programmer import UJProg # IOs ---------------------------------------------------------------------------------------------- _io_common = [ + # Clk / Rst ("clk25", 0, Pins("G2"), IOStandard("LVCMOS33")), ("rst", 0, Pins("R1"), IOStandard("LVCMOS33")), + # Leds ("user_led", 0, Pins("B2"), IOStandard("LVCMOS33")), ("user_led", 1, Pins("C2"), IOStandard("LVCMOS33")), ("user_led", 2, Pins("C1"), IOStandard("LVCMOS33")), @@ -23,11 +25,13 @@ _io_common = [ ("user_led", 6, Pins("E1"), IOStandard("LVCMOS33")), ("user_led", 7, Pins("H3"), IOStandard("LVCMOS33")), + # Serial ("serial", 0, Subsignal("tx", Pins("L4"), IOStandard("LVCMOS33")), Subsignal("rx", Pins("M1"), IOStandard("LVCMOS33")) ), + # SDR SDRAM ("sdram_clock", 0, Pins("F19"), IOStandard("LVCMOS33")), ("sdram", 0, Subsignal("a", Pins( @@ -47,11 +51,7 @@ _io_common = [ Misc("SLEWRATE=FAST"), ), - ("wifi_gpio0", 0, Pins("L2"), IOStandard("LVCMOS33")), - - ("ext0p", 0, Pins("B11"), IOStandard("LVCMOS33")), - ("ext1p", 0, Pins("A10"), IOStandard("LVCMOS33")), - + # GPIOs ("gpio", 0, Subsignal("p", Pins("B11")), Subsignal("n", Pins("C11")), @@ -73,12 +73,15 @@ _io_common = [ IOStandard("LVCMOS33") ), + # USB ("usb", 0, Subsignal("d_p", Pins("D15")), Subsignal("d_n", Pins("E15")), Subsignal("pullup", Pins("B12 C12")), IOStandard("LVCMOS33") ), + + # OLED ("oled_spi", 0, Subsignal("clk", Pins("P4")), Subsignal("mosi", Pins("P3")), @@ -90,9 +93,15 @@ _io_common = [ Subsignal("csn", Pins("N2")), IOStandard("LVCMOS33"), ), + + # Others + ("wifi_gpio0", 0, Pins("L2"), IOStandard("LVCMOS33")), + ("ext0p", 0, Pins("B11"), IOStandard("LVCMOS33")), + ("ext1p", 0, Pins("A10"), IOStandard("LVCMOS33")), ] _io_1_7 = [ + # SDCard ("spisdcard", 0, Subsignal("clk", Pins("J1")), Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")), @@ -101,7 +110,6 @@ _io_1_7 = [ Misc("SLEWRATE=FAST"), IOStandard("LVCMOS33"), ), - ("sdcard", 0, Subsignal("clk", Pins("J1")), Subsignal("cmd", Pins("J3"), Misc("PULLMODE=UP")), @@ -112,6 +120,7 @@ _io_1_7 = [ ] _io_2_0 = [ + # SDCard ("spisdcard", 0, Subsignal("clk", Pins("H2")), Subsignal("mosi", Pins("J1"), Misc("PULLMODE=UP")), @@ -120,7 +129,6 @@ _io_2_0 = [ Misc("SLEWRATE=FAST"), IOStandard("LVCMOS33"), ), - ("sdcard", 0, Subsignal("clk", Pins("H2")), Subsignal("cmd", Pins("J1"), Misc("PULLMODE=UP")), diff --git a/litex_boards/platforms/vc707.py b/litex_boards/platforms/vc707.py index 2128ab5..3cb4340 100644 --- a/litex_boards/platforms/vc707.py +++ b/litex_boards/platforms/vc707.py @@ -13,6 +13,7 @@ from litex.build.openocd import OpenOCD # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst ("clk200", 0, Subsignal("p", Pins("E19"), IOStandard("LVDS")), Subsignal("n", Pins("E18"), IOStandard("LVDS")), @@ -21,9 +22,9 @@ _io = [ Subsignal("p", Pins("AK34"), IOStandard("LVDS")), Subsignal("n", Pins("AL34"), IOStandard("LVDS")), ), - ("cpu_reset", 0, Pins("AV40"), IOStandard("LVCMOS18")), + # Leds ("user_led", 0, Pins("AM39"), IOStandard("LVCMOS18")), ("user_led", 1, Pins("AN39"), IOStandard("LVCMOS18")), ("user_led", 2, Pins("AR37"), IOStandard("LVCMOS18")), @@ -33,6 +34,7 @@ _io = [ ("user_led", 6, Pins("AP42"), IOStandard("LVCMOS18")), ("user_led", 7, Pins("AU39"), IOStandard("LVCMOS18")), + # Switches ("user_dip_btn", 0, Pins("AV30"), IOStandard("LVCMOS18")), ("user_dip_btn", 1, Pins("AY33"), IOStandard("LVCMOS18")), ("user_dip_btn", 2, Pins("BA31"), IOStandard("LVCMOS18")), @@ -42,17 +44,20 @@ _io = [ ("user_dip_btn", 6, Pins("BA30"), IOStandard("LVCMOS18")), ("user_dip_btn", 7, Pins("BB31"), IOStandard("LVCMOS18")), + # Buttons ("user_btn_c", 0, Pins("AV39"), IOStandard("LVCMOS18")), ("user_btn_n", 0, Pins("AR40"), IOStandard("LVCMOS18")), ("user_btn_e", 0, Pins("AU38"), IOStandard("LVCMOS18")), ("user_btn_s", 0, Pins("AP40"), IOStandard("LVCMOS18")), ("user_btn_w", 0, Pins("AW40"), IOStandard("LVCMOS18")), + # Serial ("serial", 0, Subsignal("rx", Pins("AU33"), IOStandard("LVCMOS18")), Subsignal("tx", Pins("AU36"), IOStandard("LVCMOS18")), ), + # Rotary Encoder ("rotary", 0, Subsignal("a", Pins("AR33")), Subsignal("b", Pins("AT31")), @@ -60,6 +65,7 @@ _io = [ IOStandard("LVCMOS18") ), + # LCD ("lcd", 0, Subsignal("db", Pins("AT42 AR38 AR39 AN40")), Subsignal("rs", Pins("AN41")), @@ -67,13 +73,16 @@ _io = [ Subsignal("e", Pins("AT40")), IOStandard("LVCMOS18") ), + + # I2C ("i2c", 0, Subsignal("scl", Pins("AT35"), IOStandard("LVCMOS18")), Subsignal("sda", Pins("AU32"), IOStandard("LVCMOS18")), ), ("i2c_mux_reset", 0, Pins("AY42"), IOStandard("LVCMOS18")), - ("mmc", 0, + # SDCard + ("sdcard", 0, Subsignal("clk", Pins("AN30")), Subsignal("cmd", Pins("AP30")), Subsignal("det", Pins("AP32")), @@ -82,12 +91,13 @@ _io = [ IOStandard("LVCMOS18"), ), - ("vadj_on_b", 0, Pins("AH35"), IOStandard("LVCMOS18")), - + # SGMII Clock ("sgmii_clock", 0, Subsignal("p", Pins("AH8")), Subsignal("n", Pins("AH7")), ), + + # SGMII Ethernet ("eth", 0, Subsignal("rst_n", Pins("AJ33"), IOStandard("LVCMOS18")), Subsignal("int_n", Pins("AL31"), IOStandard("LVCMOS18")), @@ -99,6 +109,7 @@ _io = [ Subsignal("tx_n", Pins("AN1")), ), + # PCIe ("pcie_x1", 0, Subsignal("rst_n", Pins("AV35"), IOStandard("LVCMOS18")), Subsignal("clk_p", Pins("AB8")), @@ -136,6 +147,7 @@ _io = [ Subsignal("tx_n", Pins("W1 AA1 AC1 AE1 AG1 AH3 AJ1 AK3")), ), + # SMA ("user_sma_clock", 0, Subsignal("p", Pins("AJ32"), IOStandard("LVCMOS18")), Subsignal("n", Pins("AK32"), IOStandard("LVCMOS18")), @@ -152,6 +164,10 @@ _io = [ Subsignal("p", Pins("AP4")), Subsignal("n", Pins("AP3")), ), + ("user_sma_gpio_p", 0, Pins("AN31"), IOStandard("LVCMOS18")), + ("user_sma_gpio_n", 0, Pins("AP31"), IOStandard("LVCMOS18")), + + # SI5324 Clock ("si5324", 0, Subsignal("rst_n", Pins("AT36"), IOStandard("LVCMOS18")), Subsignal("int", Pins("AU34"), IOStandard("LVCMOS18")), @@ -161,9 +177,7 @@ _io = [ Subsignal("n", Pins("AD7")), ), - ("user_sma_gpio_p", 0, Pins("AN31"), IOStandard("LVCMOS18")), - ("user_sma_gpio_n", 0, Pins("AP31"), IOStandard("LVCMOS18")), - + # HDMI ("hdmi", 0, Subsignal("d", Pins( "AM22 AL22 AJ20 AJ21 AM21 AL21 AK22 AJ22", @@ -181,6 +195,7 @@ _io = [ IOStandard("LVCMOS18"), ), + # DDR3 SDRAM ("ddram", 0, Subsignal("a", Pins( "A20 B19 C20 A19 A17 A16 D20 C18", @@ -208,36 +223,8 @@ _io = [ Misc("SLEW=FAST"), Misc("VCCAUX_IO=HIGH"), ), - ("ddram_dual_rank", 0, - Subsignal("a", Pins( - "A20 B19 C20 A19 A17 A16 D20 C18", - "D17 C19 B21 B17 A15 A21 F17 E17"), - IOStandard("SSTL15")), - Subsignal("ba", Pins("D21 C21 D18"), IOStandard("SSTL15")), - Subsignal("ras_n", Pins("E20"), IOStandard("SSTL15")), - Subsignal("cas_n", Pins("K17"), IOStandard("SSTL15")), - Subsignal("we_n", Pins("F20"), IOStandard("SSTL15")), - Subsignal("cs_n", Pins("J17 J20"), IOStandard("SSTL15")), - Subsignal("dm", Pins("M13 K15 F12 A14 C23 D25 C31 F31"), IOStandard("SSTL15")), - Subsignal("dq", Pins( - "N14 N13 L14 M14 M12 N15 M11 L12", - "K14 K13 H13 J13 L16 L15 H14 J15", - "E15 E13 F15 E14 G13 G12 F14 G14", - "B14 C13 B16 D15 D13 E12 C16 D16", - "A24 B23 B27 B26 A22 B22 A25 C24", - "E24 D23 D26 C25 E23 D22 F22 E22", - "A30 D27 A29 C28 D28 B31 A31 A32", - "E30 F29 F30 F27 C30 E29 F26 D30"), - IOStandard("SSTL15")), - Subsignal("dqs_p", Pins("N16 K12 H16 C15 A26 F25 B28 E27"), IOStandard("DIFF_SSTL15")), - Subsignal("dqs_n", Pins("M16 J12 G16 C14 A27 E25 B29 E28"), IOStandard("DIFF_SSTL15")), - Subsignal("clk_p", Pins("H19 G19"), IOStandard("DIFF_SSTL15")), - Subsignal("clk_n", Pins("G18 F19"), IOStandard("DIFF_SSTL15")), - Subsignal("cke", Pins("K19 J18"), IOStandard("SSTL15")), - Subsignal("odt", Pins("H20 H18"), IOStandard("SSTL15")), - Subsignal("reset_n", Pins("C29"), IOStandard("LVCMOS15")), - ), + # SFP ("sfp", 0, Subsignal("txp", Pins("AM4")), Subsignal("txn", Pins("AM3")), @@ -254,6 +241,9 @@ _io = [ ), ("sfp_tx_disable_n", 0, Pins("AP33"), IOStandard("LVCMOS18")), ("sfp_rx_los", 0, Pins("BB38"), IOStandard("LVCMOS18")), + + # Others + ("vadj_on_b", 0, Pins("AH35"), IOStandard("LVCMOS18")), ] # Connectors --------------------------------------------------------------------------------------- diff --git a/litex_boards/platforms/vcu118.py b/litex_boards/platforms/vcu118.py index 5257576..ab1b77d 100644 --- a/litex_boards/platforms/vcu118.py +++ b/litex_boards/platforms/vcu118.py @@ -11,6 +11,7 @@ from litex.build.xilinx import XilinxPlatform, VivadoProgrammer # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst ("clk300", 0, Subsignal("p", Pins("G31"), IOStandard("DIFF_SSTL12")), Subsignal("n", Pins("F31"), IOStandard("DIFF_SSTL12")), @@ -31,9 +32,9 @@ _io = [ Subsignal("p", Pins("H32"), IOStandard("DIFF_SSTL12")), Subsignal("n", Pins("G32"), IOStandard("DIFF_SSTL12")), ), - ("cpu_reset", 0, Pins("L19"), IOStandard("LVCMOS12")), + # Leds ("user_led", 0, Pins("AT32"), IOStandard("LVCMOS12")), ("user_led", 1, Pins("AV34"), IOStandard("LVCMOS12")), ("user_led", 2, Pins("AY30"), IOStandard("LVCMOS12")), @@ -43,23 +44,27 @@ _io = [ ("user_led", 6, Pins("AV36"), IOStandard("LVCMOS12")), ("user_led", 7, Pins("BA37"), IOStandard("LVCMOS12")), + # Switches ("user_dip_btn", 0, Pins("B17"), IOStandard("LVCMOS12")), ("user_dip_btn", 1, Pins("G16"), IOStandard("LVCMOS12")), ("user_dip_btn", 2, Pins("J16"), IOStandard("LVCMOS12")), ("user_dip_btn", 3, Pins("D21"), IOStandard("LVCMOS12")), + # Buttons ("user_btn_c", 0, Pins("BD23"), IOStandard("LVCMOS18")), ("user_btn_n", 0, Pins("BB24"), IOStandard("LVCMOS18")), ("user_btn_e", 0, Pins("BE23"), IOStandard("LVCMOS18")), ("user_btn_s", 0, Pins("BE22"), IOStandard("LVCMOS18")), ("user_btn_w", 0, Pins("BF22"), IOStandard("LVCMOS18")), + # I2C ("i2c", 0, Subsignal("scl", Pins("AM24"), IOStandard("LVCMOS18")), Subsignal("sda", Pins("AL24"), IOStandard("LVCMOS18")), ), ("i2c_mux_reset_n", 0, Pins("AL25"), IOStandard("LVCMOS18")), + # Serial ("serial", 0, Subsignal("rx", Pins("AW25"), IOStandard("LVCMOS18")), Subsignal("rts", Pins("BB22"), IOStandard("LVCMOS18")), diff --git a/litex_boards/platforms/versa_ecp5.py b/litex_boards/platforms/versa_ecp5.py index f368455..41021e0 100644 --- a/litex_boards/platforms/versa_ecp5.py +++ b/litex_boards/platforms/versa_ecp5.py @@ -12,9 +12,11 @@ from litex.build.lattice.programmer import OpenOCDJTAGProgrammer # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst ("clk100", 0, Pins("P3"), IOStandard("LVDS")), ("rst_n", 0, Pins("T1"), IOStandard("LVCMOS33")), + # Leds ("user_led", 0, Pins("E16"), IOStandard("LVCMOS25")), ("user_led", 1, Pins("D17"), IOStandard("LVCMOS25")), ("user_led", 2, Pins("D18"), IOStandard("LVCMOS25")), @@ -24,6 +26,7 @@ _io = [ ("user_led", 6, Pins("E17"), IOStandard("LVCMOS25")), ("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")), + # Switches ("user_dip_btn", 0, Pins("H2"), IOStandard("LVCMOS15")), ("user_dip_btn", 1, Pins("K3"), IOStandard("LVCMOS15")), ("user_dip_btn", 2, Pins("G3"), IOStandard("LVCMOS15")), @@ -33,11 +36,13 @@ _io = [ ("user_dip_btn", 6, Pins("K19"), IOStandard("LVCMOS25")), ("user_dip_btn", 7, Pins("K20"), IOStandard("LVCMOS25")), + # Serial ("serial", 0, Subsignal("rx", Pins("C11"), IOStandard("LVCMOS33")), Subsignal("tx", Pins("A11"), IOStandard("LVCMOS33")), ), + # SPIFlash ("spiflash", 0, # clock needs to be accessed through USRMCLK Subsignal("cs_n", Pins("R2")), Subsignal("mosi", Pins("W2")), @@ -46,13 +51,14 @@ _io = [ Subsignal("hold", Pins("W1")), IOStandard("LVCMOS33"), ), - ("spiflash4x", 0, # clock needs to be accessed through USRMCLK Subsignal("cs_n", Pins("R2")), Subsignal("dq", Pins("W2 V2 Y2 W1")), IOStandard("LVCMOS33") ), + + # DDR3 SDRAM ("ddram", 0, Subsignal("a", Pins( "P2 C4 E5 F5 B3 F4 B5 E4", @@ -79,6 +85,7 @@ _io = [ Misc("SLEWRATE=FAST"), ), + # RGMII Ethernet ("eth_clocks", 0, Subsignal("tx", Pins("P19")), Subsignal("rx", Pins("L20")), @@ -94,7 +101,6 @@ _io = [ Subsignal("tx_data", Pins("N19 N20 P18 P20")), IOStandard("LVCMOS25") ), - ("eth_clocks", 1, Subsignal("tx", Pins("C20")), Subsignal("rx", Pins("J19")), @@ -111,12 +117,7 @@ _io = [ IOStandard("LVCMOS25") ), - ("ext_clk", 0, - Subsignal("p", Pins("A4")), - Subsignal("n", Pins("A5")), - IOStandard("LVDS") - ), - + # PCIe ("pcie_x1", 0, Subsignal("clk_p", Pins("Y11")), Subsignal("clk_n", Pins("Y12")), @@ -127,6 +128,14 @@ _io = [ Subsignal("perst", Pins("A6"), IOStandard("LVCMOS33")), ), + # External Clock + ("ext_clk", 0, + Subsignal("p", Pins("A4")), + Subsignal("n", Pins("A5")), + IOStandard("LVDS") + ), + + # Ref Clock ("refclk_en", 0, Pins("C12"), IOStandard("LVCMOS33")), ("refclk_rst_n", 0, Pins("R1"), IOStandard("LVCMOS33")), ("refclk", 0, @@ -138,6 +147,7 @@ _io = [ Subsignal("n", Pins("W20")), ), + # SMA ("sma_tx", 0, Subsignal("p", Pins("W8")), Subsignal("n", Pins("W9")), @@ -148,6 +158,7 @@ _io = [ ), ] +# ECP5-hat extension (https://github.com/daveshah1/ecp5-hat) --------------------------------------- _ecp5_soc_hat_io = [ ("sdram_clock", 0, Pins("E14"), IOStandard("LVCMOS33")), diff --git a/litex_boards/platforms/xcu1525.py b/litex_boards/platforms/xcu1525.py index b16b656..f42343b 100644 --- a/litex_boards/platforms/xcu1525.py +++ b/litex_boards/platforms/xcu1525.py @@ -11,7 +11,7 @@ from litex.build.xilinx import XilinxPlatform, VivadoProgrammer # IOs ---------------------------------------------------------------------------------------------- _io = [ - # clk + # Clk / Rst ("clk300", 0, Subsignal("n", Pins("AY38"), IOStandard("DIFF_SSTL12")), Subsignal("p", Pins("AY37"), IOStandard("DIFF_SSTL12")), @@ -29,18 +29,18 @@ _io = [ Subsignal("p", Pins("J16"), IOStandard("DIFF_SSTL12")), ), - # led + # Leds ("user_led", 0, Pins("BC21"), IOStandard("LVCMOS12")), ("user_led", 1, Pins("BB21"), IOStandard("LVCMOS12")), ("user_led", 2, Pins("BA20"), IOStandard("LVCMOS12")), - # serial + # Serial ("serial", 0, Subsignal("rx", Pins("BF18"), IOStandard("LVCMOS12")), Subsignal("tx", Pins("BB20"), IOStandard("LVCMOS12")), ), - # pcie + # PCIe ("pcie_x2", 0, Subsignal("rst_n", Pins("BD21"), IOStandard("LVCMOS12")), Subsignal("clk_n", Pins("AM10")), @@ -50,7 +50,6 @@ _io = [ Subsignal("tx_n", Pins("AF6 AG8")), Subsignal("tx_p", Pins("AF7 AG9")), ), - ("pcie_x4", 0, Subsignal("rst_n", Pins("BD21"), IOStandard("LVCMOS12")), Subsignal("clk_n", Pins("AM10")), @@ -60,7 +59,6 @@ _io = [ Subsignal("tx_n", Pins("AF6 AG8 AH6 AJ8")), Subsignal("tx_p", Pins("AF7 AG9 AH7 AJ9")), ), - ("pcie_x8", 0, Subsignal("rst_n", Pins("BD21"), IOStandard("LVCMOS12")), Subsignal("clk_n", Pins("AM10")), @@ -70,7 +68,6 @@ _io = [ Subsignal("tx_n", Pins("AF6 AG8 AH6 AJ8 AK6 AL8 AM6 AN8")), Subsignal("tx_p", Pins("AF7 AG9 AH7 AJ9 AK7 AL9 AM7 AN9")), ), - ("pcie_x16", 0, Subsignal("rst_n", Pins("BD21"), IOStandard("LVCMOS12")), Subsignal("clk_n", Pins("AM10")), @@ -81,7 +78,7 @@ _io = [ Subsignal("tx_p", Pins("AF7 AG9 AH7 AJ9 AK7 AL9 AM7 AN9 AP7 AR9 AT7 AU9 AV7 BB5 BD5 BF5")), ), - # ddram + # DDR4 SDRAM ("ddram", 0, Subsignal("a", Pins( "AT36 AV36 AV37 AW35 AW36 AY36 AY35 BA40", @@ -260,6 +257,8 @@ _io = [ ), ] +# Connectors --------------------------------------------------------------------------------------- + _connectors = [] # Platform ----------------------------------------------------------------------------------------- diff --git a/litex_boards/platforms/zcu104.py b/litex_boards/platforms/zcu104.py index ffeec25..4e4b47f 100644 --- a/litex_boards/platforms/zcu104.py +++ b/litex_boards/platforms/zcu104.py @@ -11,33 +11,36 @@ from litex.build.xilinx import XilinxPlatform, VivadoProgrammer # IOs ---------------------------------------------------------------------------------------------- _io = [ + # Clk / Rst ("clk125", 0, Subsignal("p", Pins("F23"), IOStandard("LVDS")), Subsignal("n", Pins("E23"), IOStandard("LVDS")), ), - ("clk300", 0, Subsignal("p", Pins("AH18"), IOStandard("DIFF_SSTL12_DCI")), Subsignal("n", Pins("AH17"), IOStandard("DIFF_SSTL12_DCI")), ), + ("cpu_reset", 0, Pins("M11"), IOStandard("LVCMOS33")), + # Leds ("user_led", 0, Pins("D5"), IOStandard("LVCMOS33")), ("user_led", 1, Pins("D6"), IOStandard("LVCMOS33")), ("user_led", 2, Pins("A5"), IOStandard("LVCMOS33")), ("user_led", 3, Pins("B5"), IOStandard("LVCMOS33")), - ("cpu_reset", 0, Pins("M11"), IOStandard("LVCMOS33")), - + # Buttons ("user_btn", 0, Pins("B4"), IOStandard("LVCMOS33")), ("user_btn", 1, Pins("C4"), IOStandard("LVCMOS33")), ("user_btn", 2, Pins("B3"), IOStandard("LVCMOS33")), ("user_btn", 3, Pins("C3"), IOStandard("LVCMOS33")), + # Switches ("user_dip", 0, Pins("E4"), IOStandard("LVCMOS33")), ("user_dip", 1, Pins("D4"), IOStandard("LVCMOS33")), ("user_dip", 2, Pins("F5"), IOStandard("LVCMOS33")), ("user_dip", 3, Pins("F4"), IOStandard("LVCMOS33")), + # Serial ("serial", 0, Subsignal("cts", Pins("A19")), Subsignal("rts", Pins("C18")), @@ -46,12 +49,14 @@ _io = [ IOStandard("LVCMOS18") ), + # I2C ("i2c", 0, Subsignal("sda", Pins("P12")), Subsignal("scl", Pins("N12")), IOStandard("LVCMOS33") ), + # DDR4 SDRAM ("ddram", 0, Subsignal("a", Pins( "AH16 AG14 AG15 AF15 AF16 AJ14 AH14 AF17", diff --git a/litex_boards/platforms/zedboard.py b/litex_boards/platforms/zedboard.py index 037e88c..43d8c80 100644 --- a/litex_boards/platforms/zedboard.py +++ b/litex_boards/platforms/zedboard.py @@ -5,8 +5,13 @@ from litex.build.generic_platform import Pins, IOStandard, Subsignal from litex.build.xilinx import XilinxPlatform from litex.build.openocd import OpenOCD +# IOs ---------------------------------------------------------------------------------------------- + _io = [ - # 8 LEDs above DIP switches (Bank 33) + # Clk / Rst + ("clk100", 0, Pins("Y9"), IOStandard("LVCMOS33")), + + # Leds (above DIP switches) ("user_led", 0, Pins("T22"), IOStandard("LVCMOS33")), ("user_led", 1, Pins("T21"), IOStandard("LVCMOS33")), ("user_led", 2, Pins("U22"), IOStandard("LVCMOS33")), @@ -16,19 +21,7 @@ _io = [ ("user_led", 6, Pins("U19"), IOStandard("LVCMOS33")), ("user_led", 7, Pins("U14"), IOStandard("LVCMOS33")), - # UG-2832HSWEG04 (ssd1306) - ("zed_oled", 0, - Subsignal("clk", Pins("AB12")), - Subsignal("mosi", Pins("AA12")), - # OLED does not have a MISO pin :( - Subsignal("reset_n", Pins("U9")), - Subsignal("dc", Pins("U10")), - Subsignal("vbat_n", Pins("U11")), - Subsignal("vdd_n", Pins("U12")), - IOStandard("LVCMOS33") - ), - - # 8 Switches (Bank 35) + # Switches ("user_sw", 0, Pins("F22"), IOStandard("LVCMOS18")), ("user_sw", 1, Pins("G22"), IOStandard("LVCMOS18")), ("user_sw", 2, Pins("H22"), IOStandard("LVCMOS18")), @@ -38,17 +31,31 @@ _io = [ ("user_sw", 6, Pins("H17"), IOStandard("LVCMOS18")), ("user_sw", 7, Pins("M15"), IOStandard("LVCMOS18")), - # push buttons (Bank 34) - # ("user_btn", 0, Pins("D13"), IOStandard("LVCMOS18")), - # ("user_btn", 1, Pins("C10"), IOStandard("LVCMOS18")), + # Buttons ("user_btn_c", 0, Pins("P16"), IOStandard("LVCMOS25")), ("user_btn_d", 0, Pins("R16"), IOStandard("LVCMOS25")), ("user_btn_l", 0, Pins("N15"), IOStandard("LVCMOS25")), ("user_btn_r", 0, Pins("R18"), IOStandard("LVCMOS25")), ("user_btn_u", 0, Pins("T18"), IOStandard("LVCMOS25")), - # Clock source (Bank 13) - ("clk100", 0, Pins("Y9"), IOStandard("LVCMOS33")), + # Serial (ust to make CI pass) + # Unfortunately the only USB UART is hard-wired to the ARM CPU + ("serial", 0, + Subsignal("tx", Pins("-")), + Subsignal("rx", Pins("-")) + ), + + # OLED (UG-2832HSWEG04/ssd1306) + ("zed_oled", 0, + Subsignal("clk", Pins("AB12")), + Subsignal("mosi", Pins("AA12")), + # OLED does not have a MISO pin :( + Subsignal("reset_n", Pins("U9")), + Subsignal("dc", Pins("U10")), + Subsignal("vbat_n", Pins("U11")), + Subsignal("vdd_n", Pins("U12")), + IOStandard("LVCMOS33") + ), # PS7 ("ps7_clk", 0, Pins("F7")), @@ -88,15 +95,9 @@ _io = [ Subsignal("vrp", Pins("N7")), Subsignal("we_n", Pins("R4")) ), - - # serial (just to make CI pass) - # unfortunately the only USB UART is hard-wired to the ARM CPU - ("serial", 0, - Subsignal("tx", Pins("-")), - Subsignal("rx", Pins("-")) - ) ] +# Connectors --------------------------------------------------------------------------------------- _connectors = [ # access a pin with `pmoda:N`, where N is: @@ -204,6 +205,7 @@ _connectors = [ }) ] +# Platform ----------------------------------------------------------------------------------------- class Platform(XilinxPlatform): default_clk_name = "clk100" diff --git a/litex_boards/platforms/zybo_z7.py b/litex_boards/platforms/zybo_z7.py index 7b44d9e..ed31d71 100644 --- a/litex_boards/platforms/zybo_z7.py +++ b/litex_boards/platforms/zybo_z7.py @@ -10,28 +10,28 @@ from litex.build.xilinx import XilinxPlatform, VivadoProgrammer # IOs ---------------------------------------------------------------------------------------------- _io = [ - # clk125 + # Clk / Rst ("clk125", 0, Pins("L16"), IOStandard("LVCMOS33")), - # user led + # Leds ("user_led", 0, Pins("M14"), IOStandard("LVCMOS33")), ("user_led", 1, Pins("M15"), IOStandard("LVCMOS33")), ("user_led", 2, Pins("G14"), IOStandard("LVCMOS33")), ("user_led", 3, Pins("D18"), IOStandard("LVCMOS33")), - # user sw + # Switches ("user_sw", 0, Pins("G15"), IOStandard("LVCMOS33")), ("user_sw", 1, Pins("P15"), IOStandard("LVCMOS33")), ("user_sw", 2, Pins("W13"), IOStandard("LVCMOS33")), ("user_sw", 3, Pins("T16"), IOStandard("LVCMOS33")), - # user btn + # Buttons ("user_btn", 0, Pins("R18"), IOStandard("LVCMOS33")), ("user_btn", 1, Pins("P16"), IOStandard("LVCMOS33")), ("user_btn", 2, Pins("V16"), IOStandard("LVCMOS33")), ("user_btn", 3, Pins("Y16"), IOStandard("LVCMOS33")), - # serial + # Serial ("serial", 0, Subsignal("tx", Pins("T17")), Subsignal("rx", Pins("Y17")), @@ -40,7 +40,7 @@ _io = [ ] _ps7_io = [ - # ps7 + # PS7 ("ps7_clk", 0, Pins(1)), ("ps7_porb", 0, Pins(1)), ("ps7_srstb", 0, Pins(1)), diff --git a/litex_boards/targets/logicbone.py b/litex_boards/targets/logicbone.py index ac9fa59..beff7fd 100755 --- a/litex_boards/targets/logicbone.py +++ b/litex_boards/targets/logicbone.py @@ -43,7 +43,7 @@ class _CRG(Module): self.reset = Signal() # Clk / Rst - clk25 = platform.request("refclk") + clk25 = platform.request("clk25") # Power on reset por_count = Signal(16, reset=2**16-1) -- 2.30.2