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Commit c093d0d0 authored by Florent Kermarrec's avatar Florent Kermarrec
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platforms: cleanup pass to uniformize comments/separators/orders.

parent 8d26c241
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Showing with 894 additions and 681 deletions
litex_boards/platforms/ac701.py
View file @ c093d0d0
......@@ -11,23 +11,24 @@ from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
("user_led", 0, Pins("M26"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("T24"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("T25"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("R26"), IOStandard("LVCMOS33")),
("cpu_reset", 0, Pins("U4"), IOStandard("SSTL15")),
# Clk / Rst
("clk200", 0,
Subsignal("p", Pins("R3"), IOStandard("DIFF_SSTL15")),
Subsignal("n", Pins("P3"), IOStandard("DIFF_SSTL15"))
),
("clk156", 0,
Subsignal("p", Pins("M21"), IOStandard("LVDS_25")),
Subsignal("n", Pins("M22"), IOStandard("LVDS_25"))
),
("cpu_reset", 0, Pins("U4"), IOStandard("SSTL15")),
# Leds
("user_led", 0, Pins("M26"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("T24"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("T25"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("R26"), IOStandard("LVCMOS33")),
# Serial
("serial", 0,
Subsignal("cts", Pins("V19")),
Subsignal("rts", Pins("W19")),
......@@ -36,12 +37,12 @@ _io = [
IOStandard("LVCMOS18")
),
# RGMII Ethernet
("eth_clocks", 0,
Subsignal("tx", Pins("U22")),
Subsignal("rx", Pins("U21")),
IOStandard("LVCMOS18")
),
("eth", 0,
Subsignal("rx_ctl", Pins("U14")),
Subsignal("rx_data", Pins("U17 V17 V16 V14")),
......@@ -55,6 +56,7 @@ _io = [
IOStandard("LVCMOS18"),
),
# DDR3 SDRAM
("ddram", 0,
Subsignal("a", Pins(
"M4 J3 J1 L4 K5 M7 K1 M6",
......@@ -90,6 +92,7 @@ _io = [
Misc("SLEW=FAST"),
),
# PCIe
("pcie_x1", 0,
Subsignal("rst_n", Pins("M20"), IOStandard("LVCMOS25")),
Subsignal("clk_p", Pins("F11")),
......@@ -100,13 +103,13 @@ _io = [
Subsignal("tx_n", Pins("C10"))
),
("vadj_on_b", 0, Pins("R16"), IOStandard("LVCMOS25")),
# GTP RefClk
("gtp_refclk", 0,
Subsignal("p", Pins("AA13")),
Subsignal("n", Pins("AB13"))
),
# SFP
("sfp", 0,
Subsignal("txp", Pins("AC10")),
Subsignal("txn", Pins("AD10")),
......@@ -117,6 +120,10 @@ _io = [
("sfp_mgt_clk_sel1", 0, Pins("C24"), IOStandard("LVCMOS25")),
("sfp_tx_disable_n", 0, Pins("R18"), IOStandard("LVCMOS33")),
("sfp_rx_los", 0, Pins("R23"), IOStandard("LVCMOS33")),
# Others
("vadj_on_b", 0, Pins("R16"), IOStandard("LVCMOS25")),
]
# Connectors ---------------------------------------------------------------------------------------
......
litex_boards/platforms/acorn_cle_215.py
View file @ c093d0d0
......@@ -14,19 +14,19 @@ from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
# clk / rst
# Clk / Rst
("clk200", 0,
Subsignal("p", Pins("J19"), IOStandard("DIFF_SSTL15")),
Subsignal("n", Pins("H19"), IOStandard("DIFF_SSTL15"))
),
# leds
# Leds
("user_led", 0, Pins("G3"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("H3"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("G4"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("H4"), IOStandard("LVCMOS33")),
# spiflash
# SPIFlash
("spiflash", 0,
Subsignal("cs_n", Pins("T19")),
Subsignal("mosi", Pins("P22")),
......@@ -36,7 +36,7 @@ _io = [
IOStandard("LVCMOS33")
),
# pcie
# PCIe
("pcie_clkreq_n", 0, Pins("G1"), IOStandard("LVCMOS33")),
("pcie_x4", 0,
Subsignal("rst_n", Pins("J1"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
......@@ -48,7 +48,7 @@ _io = [
Subsignal("tx_n", Pins("A6 A4 C5 C7")),
),
# dram
# DDR3 SDRAM
("ddram", 0,
Subsignal("a", Pins(
"M15 L21 M16 L18 K21 M18 M21 N20",
......
litex_boards/platforms/aller.py
View file @ c093d0d0
......@@ -12,15 +12,15 @@ from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
# clk / rst
# Clk / Rst
("clk100", 0, Pins("W19"), IOStandard("LVCMOS33")),
# leds (only a single rgb led, aliased here also)
# Leds (only a single rgb led, aliased here also)
("user_led", 0, Pins("AB21"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("AB22"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("U20"), IOStandard("LVCMOS33")),
# rgb led, active-low
# RGB led, active-low
("rgb_led", 0,
Subsignal("r", Pins("AB21")),
Subsignal("g", Pins("AB22")),
......@@ -28,7 +28,7 @@ _io = [
IOStandard("LVCMOS33"),
),
# flash
# SPIFlash
("flash", 0,
Subsignal("cs_n", Pins("T19")),
Subsignal("mosi", Pins("P22")),
......@@ -37,14 +37,13 @@ _io = [
Subsignal("rst_n", Pins("R19")),
IOStandard("LVCMOS33")
),
("flash4x", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("T19")),
Subsignal("dq", Pins("P22", "R22", "P21", "R21")),
IOStandard("LVCMOS33")
),
# tpm
# TPM
("tpm", 0,
Subsignal("clk", Pins("W20")),
Subsignal("rst_n", Pins("V19")),
......@@ -54,7 +53,7 @@ _io = [
IOStandard("LVCMOS33"),
),
# pcie
# PCIe
("pcie_x1", 0,
Subsignal("rst_n", Pins("AB20"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
Subsignal("clk_p", Pins("F6")),
......@@ -75,7 +74,7 @@ _io = [
Subsignal("tx_n", Pins("A4 C5 A6 C7"))
),
# dram
# DDR3 SDRAM
("ddram", 0,
Subsignal("a", Pins(
"U6 T5 Y6 T6 V2 T4 Y2 R2",
......
litex_boards/platforms/alveo_u250.py
View file @ c093d0d0
......@@ -14,7 +14,7 @@ from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs (initially auto-generated by extract_xdc_pins.py) ---------------------------------------------
_io = [
# clk / rst
# Clk / Rst
("clk300", 0,
Subsignal("n", Pins("AY38"), IOStandard("DIFF_SSTL12")),
Subsignal("p", Pins("AY37"), IOStandard("DIFF_SSTL12")),
......@@ -33,24 +33,25 @@ _io = [
),
("cpu_reset", 0, Pins("AL20"), IOStandard("LVCMOS12")),
# led
# Leds
("user_led", 0, Pins("BC21"), IOStandard("LVCMOS12")),
("user_led", 1, Pins("BB21"), IOStandard("LVCMOS12")),
("user_led", 2, Pins("BA20"), IOStandard("LVCMOS12")),
# switches
# Switches
("set_sw", 0, Pins("AL21")),
("user_sw", 0, Pins("AN22"), IOStandard("LVCMOS12")),
("user_sw", 1, Pins("AM19"), IOStandard("LVCMOS12")),
("user_sw", 2, Pins("AL19"), IOStandard("LVCMOS12")),
("user_sw", 3, Pins("AP20"), IOStandard("LVCMOS12")),
# gpio
# GPIOs
("gpio_msp", 0, Pins("AR20"), IOStandard("LVCMOS12")),
("gpio_msp", 1, Pins("AM20"), IOStandard("LVCMOS12")),
("gpio_msp", 2, Pins("AM21"), IOStandard("LVCMOS12")),
("gpio_msp", 3, Pins("AN21"), IOStandard("LVCMOS12")),
# Serial
("serial", 0,
Subsignal("rx", Pins("BF18"), IOStandard("LVCMOS12")),
Subsignal("tx", Pins("BB20"), IOStandard("LVCMOS12")),
......@@ -60,7 +61,7 @@ _io = [
Subsignal("tx", Pins("BB19"), IOStandard("LVCMOS12")),
),
# ddram
# DDR4 SDRAM
("ddram_reset_gate", 0, Pins("AU21"), IOStandard("LVCMOS12")),
("ddram", 0,
Subsignal("a", Pins(
......@@ -235,14 +236,14 @@ _io = [
Misc("SLEW=FAST")
),
# i2c
# I2C
("i2c_rst_n", 0, Pins("BF19"), IOStandard("LVCMOS12")),
("i2c", 0,
Subsignal("scl", Pins("BF20"), IOStandard("LVCMOS12")),
Subsignal("sda", Pins("BF17"), IOStandard("LVCMOS12")),
),
# si570
# SI570 Clock
("user_si570_clock", 0,
Subsignal("n", Pins("AV19"), IOStandard("DIFF_SSTL12")),
Subsignal("p", Pins("AU19"), IOStandard("DIFF_SSTL12")),
......@@ -256,7 +257,7 @@ _io = [
Subsignal("p", Pins("T11")),
),
# pcie
# PCIe
("pcie_x16", 0,
Subsignal("rst_n", Pins("BD21"), IOStandard("LVCMOS12")),
Subsignal("clk_n", Pins("AM10")),
......@@ -275,7 +276,7 @@ _io = [
"AP7 AR9 AT7 AU9 AV7 BB5 BD5 BF5")),
),
# pcie
# PCIe
("pcie_x4", 0,
Subsignal("rst_n", Pins("BD21"), IOStandard("LVCMOS12")),
Subsignal("clk_n", Pins("AM10")),
......@@ -286,7 +287,7 @@ _io = [
Subsignal("tx_p", Pins("AF7 AG9 AH7 AJ9")),
),
# qsfp28
# QSFP28
("qsfp28", 0,
Subsignal("clk_n", Pins("K10")),
Subsignal("clk_p", Pins("K11")),
......@@ -321,6 +322,8 @@ _io = [
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = []
# Platform -----------------------------------------------------------------------------------------
......
litex_boards/platforms/arty.py
View file @ c093d0d0
......@@ -12,6 +12,12 @@ from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk100", 0, Pins("E3"), IOStandard("LVCMOS33")),
("cpu_reset", 0, Pins("C2"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("H5"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("J5"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("T9"), IOStandard("LVCMOS33")),
......@@ -23,21 +29,18 @@ _io = [
Subsignal("b", Pins("E1")),
IOStandard("LVCMOS33"),
),
("rgb_led", 1,
Subsignal("r", Pins("G3")),
Subsignal("g", Pins("J4")),
Subsignal("b", Pins("G4")),
IOStandard("LVCMOS33"),
),
("rgb_led", 2,
Subsignal("r", Pins("J3")),
Subsignal("g", Pins("J2")),
Subsignal("b", Pins("H4")),
IOStandard("LVCMOS33"),
),
("rgb_led", 3,
Subsignal("r", Pins("K1")),
Subsignal("g", Pins("H6")),
......@@ -45,26 +48,26 @@ _io = [
IOStandard("LVCMOS33"),
),
# Switches
("user_sw", 0, Pins("A8"), IOStandard("LVCMOS33")),
("user_sw", 1, Pins("C11"), IOStandard("LVCMOS33")),
("user_sw", 2, Pins("C10"), IOStandard("LVCMOS33")),
("user_sw", 3, Pins("A10"), IOStandard("LVCMOS33")),
# Buttons
("user_btn", 0, Pins("D9"), IOStandard("LVCMOS33")),
("user_btn", 1, Pins("C9"), IOStandard("LVCMOS33")),
("user_btn", 2, Pins("B9"), IOStandard("LVCMOS33")),
("user_btn", 3, Pins("B8"), IOStandard("LVCMOS33")),
("clk100", 0, Pins("E3"), IOStandard("LVCMOS33")),
("cpu_reset", 0, Pins("C2"), IOStandard("LVCMOS33")),
# Serial
("serial", 0,
Subsignal("tx", Pins("D10")),
Subsignal("rx", Pins("A9")),
IOStandard("LVCMOS33")
),
# SPI
("spi", 0,
Subsignal("clk", Pins("F1")),
Subsignal("cs_n", Pins("C1")),
......@@ -73,6 +76,7 @@ _io = [
IOStandard("LVCMOS33"),
),
# I2C
("i2c", 0,
Subsignal("scl", Pins("L18")),
Subsignal("sda", Pins("M18")),
......@@ -81,12 +85,7 @@ _io = [
IOStandard("LVCMOS33"),
),
("spiflash4x", 0,
Subsignal("cs_n", Pins("L13")),
Subsignal("clk", Pins("L16")),
Subsignal("dq", Pins("K17", "K18", "L14", "M14")),
IOStandard("LVCMOS33")
),
# SPIFlash
("spiflash", 0,
Subsignal("cs_n", Pins("L13")),
Subsignal("clk", Pins("L16")),
......@@ -96,7 +95,14 @@ _io = [
Subsignal("hold", Pins("M14")),
IOStandard("LVCMOS33"),
),
("spiflash4x", 0,
Subsignal("cs_n", Pins("L13")),
Subsignal("clk", Pins("L16")),
Subsignal("dq", Pins("K17", "K18", "L14", "M14")),
IOStandard("LVCMOS33")
),
# DDR3 SDRAM
("ddram", 0,
Subsignal("a", Pins(
"R2 M6 N4 T1 N6 R7 V6 U7",
......@@ -127,6 +133,7 @@ _io = [
Misc("SLEW=FAST"),
),
# MII Ethernet
("eth_ref_clk", 0, Pins("G18"), IOStandard("LVCMOS33")),
("eth_clocks", 0,
Subsignal("tx", Pins("H16")),
......
litex_boards/platforms/arty_s7.py
View file @ c093d0d0
......@@ -12,6 +12,11 @@ from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk100", 0, Pins("R2"), IOStandard("SSTL135")),
("cpu_reset", 0, Pins("C18"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("E18"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("F13"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("E13"), IOStandard("LVCMOS33")),
......@@ -23,7 +28,6 @@ _io = [
Subsignal("b", Pins("F15")),
IOStandard("LVCMOS33")
),
("rgb_led", 1,
Subsignal("r", Pins("E15")),
Subsignal("g", Pins("F18")),
......@@ -31,6 +35,7 @@ _io = [
IOStandard("LVCMOS33")
),
# Switches
("user_sw", 0, Pins("H14"), IOStandard("LVCMOS33")),
("user_sw", 1, Pins("H18"), IOStandard("LVCMOS33")),
("user_sw", 2, Pins("G18"), IOStandard("LVCMOS33")),
......@@ -41,15 +46,14 @@ _io = [
("user_btn", 2, Pins("J16"), IOStandard("LVCMOS33")),
("user_btn", 3, Pins("H13"), IOStandard("LVCMOS33")),
("clk100", 0, Pins("R2"), IOStandard("SSTL135")),
("cpu_reset", 0, Pins("C18"), IOStandard("LVCMOS33")),
# Serial
("serial", 0,
Subsignal("tx", Pins("R12")),
Subsignal("rx", Pins("V12")),
IOStandard("LVCMOS33")),
IOStandard("LVCMOS33")
),
# SPI
("spi", 0,
Subsignal("clk", Pins("G16")),
Subsignal("cs_n", Pins("H16")),
......@@ -58,18 +62,14 @@ _io = [
IOStandard("LVCMOS33")
),
# I2C
("i2c", 0,
Subsignal("scl", Pins("J14")),
Subsignal("sda", Pins("J13")),
IOStandard("LVCMOS33"),
),
("spiflash4x", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("M13")),
Subsignal("clk", Pins("D11")),
Subsignal("dq", Pins("K17", "K18", "L14", "M15")),
IOStandard("LVCMOS33")
),
# SPIFlash
("spiflash", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("M13")),
Subsignal("clk", Pins("D11")),
......@@ -79,7 +79,14 @@ _io = [
Subsignal("hold", Pins("M15")),
IOStandard("LVCMOS33")
),
("spiflash4x", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("M13")),
Subsignal("clk", Pins("D11")),
Subsignal("dq", Pins("K17", "K18", "L14", "M15")),
IOStandard("LVCMOS33")
),
# DDR3 SDRAM
("ddram", 0,
Subsignal("a", Pins(
"U2 R4 V2 V4 T3 R7 V6 T6",
......
litex_boards/platforms/avalanche.py
View file @ c093d0d0
......@@ -10,31 +10,29 @@ from litex.build.microsemi import MicrosemiPlatform
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk50", 0, Pins("R1"), IOStandard("LVCMOS25")),
("clk50", 1, Pins("J3"), IOStandard("LVCMOS25")),
("rst_n", 0, Pins("F5"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("D6"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("D7"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("D8"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("D9"), IOStandard("LVCMOS33")),
# Buttons
("user_btn", 0, Pins("E13"), IOStandard("LVCMOS33")),
("user_btn", 1, Pins("E14"), IOStandard("LVCMOS33")),
# Serial
("serial", 0,
Subsignal("tx", Pins("F17")),
Subsignal("rx", Pins("F16")),
IOStandard("LVCMOS33")
),
("spiflash4x", 0,
Subsignal("clk", Pins("J1")),
Subsignal("cs_n", Pins("H1")),
Subsignal("dq", Pins("F2 F1 M7 M8")),
IOStandard("LVCMOS25")
),
# SPIFlash
("spiflash", 0,
Subsignal("clk", Pins("J1")),
Subsignal("cs_n", Pins("H1")),
......@@ -44,7 +42,14 @@ _io = [
Subsignal("hold", Pins("M8")),
IOStandard("LVCMOS25"),
),
("spiflash4x", 0,
Subsignal("clk", Pins("J1")),
Subsignal("cs_n", Pins("H1")),
Subsignal("dq", Pins("F2 F1 M7 M8")),
IOStandard("LVCMOS25")
),
# DDR3 SDRAM
("ddram", 0,
Subsignal("a", Pins(
"U5 U4 V4 W3 V5 W4 Y3 AA3",
......@@ -69,6 +74,7 @@ _io = [
Subsignal("reset_n", Pins("AB7"), IOStandard("SSTL15II")),
),
# Ethernet
("eth_clocks", 0,
Subsignal("tx", Pins("J8")),
Subsignal("rx", Pins("K3")),
......
litex_boards/platforms/c10lprefkit.py
View file @ c093d0d0
......@@ -12,28 +12,32 @@ from litex.build.altera.programmer import USBBlaster
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk12", 0, Pins("G21"), IOStandard("3.3-V LVTTL")),
("clk25", 0, Pins("AA12"), IOStandard("3.3-V LVTTL")),
("cpu_reset", 0, Pins("V15"), IOStandard("3.3-V LVTTL")),
# Leds
("user_led", 0, Pins("C18"), IOStandard("3.3-V LVTTL")),
("user_led", 1, Pins("D19"), IOStandard("3.3-V LVTTL")),
("user_led", 2, Pins("C19"), IOStandard("3.3-V LVTTL")),
("user_led", 3, Pins("C17"), IOStandard("3.3-V LVTTL")),
("user_led", 4, Pins("D18"), IOStandard("3.3-V LVTTL")),
("cpu_reset", 0, Pins("V15"), IOStandard("3.3-V LVTTL")),
# Switches
("sw", 0, Pins("U10"), IOStandard("3.3-V LVTTL")),
("sw", 1, Pins("U11"), IOStandard("3.3-V LVTTL")),
("sw", 2, Pins("V11"), IOStandard("3.3-V LVTTL")),
("sw", 3, Pins("T10"), IOStandard("3.3-V LVTTL")),
("sw", 4, Pins("T11"), IOStandard("3.3-V LVTTL")),
# Serial
("serial", 0,
Subsignal("tx", Pins("B21"), IOStandard("3.3-V LVTTL")),
Subsignal("rx", Pins("C20"), IOStandard("3.3-V LVTTL")),
),
# SDR SDRAM
("sdram_clock", 0, Pins("AA3"), IOStandard("3.3-V LVTTL")),
("sdram", 0,
Subsignal("a", Pins(
......@@ -52,14 +56,16 @@ _io = [
IOStandard("3.3-V LVTTL")
),
# ECPS
("epcs", 0,
Subsignal("data0", Pins("K1")),
Subsignal("dclk", Pins("K2")),
Subsignal("ncs0", Pins("E2")),
Subsignal("asd0", Pins("D1")),
Subsignal("dclk", Pins("K2")),
Subsignal("ncs0", Pins("E2")),
Subsignal("asd0", Pins("D1")),
IOStandard("3.3-V LVTTL")
),
# HyperRAM
("hyperram", 0,
Subsignal("clk", Pins("T16")),
Subsignal("rst_n", Pins("U12")),
......@@ -69,11 +75,13 @@ _io = [
IOStandard("3.3-V LVTTL")
),
# GPIO Leds
("gpio_leds", 0,
Pins("AB10 AA10 AA9 Y10 W10 U9 U8 U7"),
IOStandard("3.3-V LVTTL")
),
# MII Ethernet
("eth_clocks", 0,
Subsignal("tx", Pins("U21")),
Subsignal("rx", Pins("V22")),
......@@ -92,7 +100,6 @@ _io = [
Subsignal("crs", Pins("R20")),
IOStandard("3.3-V LVTTL"),
),
("eth_clocks", 1,
Subsignal("tx", Pins("N16")),
Subsignal("rx", Pins("V22")),
......
litex_boards/platforms/camlink_4k.py
View file @ c093d0d0
......@@ -16,17 +16,21 @@ from litex.build.lattice import LatticePlatform
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk27", 0, Pins("B11"), IOStandard("LVCMOS25")),
# Leds
("user_led", 0, Pins("A6"), IOStandard("LVCMOS25")),
("user_led", 1, Pins("A9"), IOStandard("LVCMOS25")),
# Serial
("serial", 0,
Subsignal("tx", Pins("A6")), # led0
Subsignal("rx", Pins("A9")), # led1
IOStandard("LVCMOS25")
),
# DDR3 SDRAM
("ddram", 0,
Subsignal("a", Pins(
"P2 L2 N1 P1 N5 M1 M3 N4",
......
litex_boards/platforms/colorlight_5a_75b.py
View file @ c093d0d0
......@@ -14,16 +14,16 @@ from litex.build.lattice.programmer import OpenOCDJTAGProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io_v6_1 = [ # Documented by @smunaut
# clock
# Clk
("clk25", 0, Pins("P3"), IOStandard("LVCMOS33")),
# led
# Led
("user_led_n", 0, Pins("U16"), IOStandard("LVCMOS33")),
# btn
# Button
("user_btn_n", 0, Pins("R16"), IOStandard("LVCMOS33")),
# serial
# Serial
# There seems to be some capacitance on KEY+ pin, so high baudrates may not work (>9600bps).
("serial", 0,
Subsignal("tx", Pins("U16")), # led (J19 DATA_LED-)
......@@ -31,7 +31,7 @@ _io_v6_1 = [ # Documented by @smunaut
IOStandard("LVCMOS33")
),
# spi flash (GD25Q16CSIG)
# SPIFlash (GD25Q16CSIG)
("spiflash", 0,
Subsignal("cs_n", Pins("R2")),
Subsignal("clk", Pins("U3")),
......@@ -40,7 +40,7 @@ _io_v6_1 = [ # Documented by @smunaut
IOStandard("LVCMOS33"),
),
# sdram (EM636165-6G)
# SDRAM SDRAM (EM636165-6G)
("sdram_clock", 0, Pins("B9"), IOStandard("LVCMOS33")),
("sdram", 0,
Subsignal("a", Pins(
......@@ -62,7 +62,7 @@ _io_v6_1 = [ # Documented by @smunaut
Misc("SLEWRATE=FAST")
),
# ethernet (B50612D)
# RGMII Ethernet (B50612D)
("eth_clocks", 0,
Subsignal("tx", Pins("G1")),
Subsignal("rx", Pins("H2")),
......@@ -78,7 +78,6 @@ _io_v6_1 = [ # Documented by @smunaut
Subsignal("tx_data", Pins("G2 H1 J1 J3")),
IOStandard("LVCMOS33")
),
("eth_clocks", 1,
Subsignal("tx", Pins("U19")),
Subsignal("rx", Pins("L19")),
......@@ -97,23 +96,23 @@ _io_v6_1 = [ # Documented by @smunaut
]
_io_v7_0 = [ # Documented by @miek
# clock
# Clk
("clk25", 0, Pins("P6"), IOStandard("LVCMOS33")),