targets: cleanup, uniformize build arguments between targets.

litex_boards/targets/ac701.py

@@ -132,10 +132,10 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on AC701")
     builder_args(parser)
     soc_sdram_args(parser)
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--load",  action="store_true", help="Load bitstream")
+    parser.add_argument("--build",         action="store_true", help="Build bitstream")
+    parser.add_argument("--load",          action="store_true", help="Load bitstream")
     parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
-    parser.add_argument("--ethernet-phy",  default="rgmii",     help="Select Ethernet PHY (rgmii or 1000basex)")
+    parser.add_argument("--ethernet-phy",  default="rgmii",     help="Select Ethernet PHY: rgmii (default) or 1000basex")
     args = parser.parse_args()
 
     soc = BaseSoC(with_ethernet=args.with_ethernet, ethernet_phy=args.ethernet_phy, **soc_sdram_argdict(args))

litex_boards/targets/acorn_cle_215.py

@@ -165,7 +165,7 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Acorn CLE 215+")
     parser.add_argument("--build",           action="store_true", help="Build bitstream")
     parser.add_argument("--with-pcie",       action="store_true", help="Enable PCIe support")
-    parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support (requires adapter off P2)")
+    parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support (requires SDCard adapter on P2)")
     parser.add_argument("--driver",          action="store_true", help="Generate PCIe driver")
     parser.add_argument("--load",            action="store_true", help="Load bitstream")
     parser.add_argument("--flash",           action="store_true", help="Flash bitstream")

litex_boards/targets/alveo_u250.py

@@ -142,10 +142,10 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Alveo U250")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
+    parser.add_argument("--build",     action="store_true", help="Build bitstream")
     parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
     parser.add_argument("--driver",    action="store_true", help="Generate PCIe driver")
-    parser.add_argument("--load",  action="store_true", help="Load bitstream")
+    parser.add_argument("--load",      action="store_true", help="Load bitstream")
     builder_args(parser)
     soc_sdram_args(parser)
     args = parser.parse_args()

litex_boards/targets/arty.py

@@ -104,15 +104,15 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--load",  action="store_true", help="Load bitstream")
-    builder_args(parser)
-    soc_sdram_args(parser)
-    vivado_build_args(parser)
+    parser.add_argument("--build",           action="store_true", help="Build bitstream")
+    parser.add_argument("--load",            action="store_true", help="Load bitstream")
     parser.add_argument("--with-ethernet",   action="store_true", help="Enable Ethernet support")
     parser.add_argument("--with-etherbone",  action="store_true", help="Enable Etherbone support")
     parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
     parser.add_argument("--with-sdcard",     action="store_true", help="Enable SDCard support")
+    builder_args(parser)
+    soc_sdram_args(parser)
+    vivado_build_args(parser)
     args = parser.parse_args()
 
     assert not (args.with_ethernet and args.with_etherbone)

litex_boards/targets/c10lprefkit.py

@@ -107,11 +107,11 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on C10 LP RefKit")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--load",  action="store_true", help="Load bitstream")
+    parser.add_argument("--build",         action="store_true", help="Build bitstream")
+    parser.add_argument("--load",          action="store_true", help="Load bitstream")
+    parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
     builder_args(parser)
     soc_sdram_args(parser)
-    parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
     args = parser.parse_args()
 
     soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args))

litex_boards/targets/camlink_4k.py

@@ -113,9 +113,9 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Cam Link 4K")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--load",  action="store_true", help="Load bitstream")
-    parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
+    parser.add_argument("--build",     action="store_true", help="Build bitstream")
+    parser.add_argument("--load",      action="store_true", help="Load bitstream")
+    parser.add_argument("--toolchain", default="trellis",   help="FPGA toolchain: trellis (default) or diamond")
     builder_args(parser)
     soc_sdram_args(parser)
     trellis_args(parser)

litex_boards/targets/colorlight_5a_75x.py

@@ -175,19 +175,19 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Colorlight 5A-75X")
-    builder_args(parser)
-    soc_core_args(parser)
-    trellis_args(parser)
     parser.add_argument("--build",            action="store_true",      help="Build bitstream")
     parser.add_argument("--load",             action="store_true",      help="Load bitstream")
     parser.add_argument("--board",            default="5a-75b",         help="Board type: 5a-75b (default) or 5a-75e")
-    parser.add_argument("--revision",         default="7.0", type=str,  help="Board revision 7.0 (default), 6.0 or 6.1")
+    parser.add_argument("--revision",         default="7.0", type=str,  help="Board revision: 7.0 (default), 6.0 or 6.1")
     parser.add_argument("--with-ethernet",    action="store_true",      help="Enable Ethernet support")
     parser.add_argument("--with-etherbone",   action="store_true",      help="Enable Etherbone support")
-    parser.add_argument("--eth-phy",          default=0, type=int,      help="Ethernet PHY 0 or 1 (default=0)")
-    parser.add_argument("--sys-clk-freq",     default=60e6, type=float, help="System clock frequency (default=60MHz)")
+    parser.add_argument("--eth-phy",          default=0, type=int,      help="Ethernet PHY: 0 (default) or 1")
+    parser.add_argument("--sys-clk-freq",     default=60e6, type=float, help="System clock frequency (default: 60MHz)")
     parser.add_argument("--use-internal-osc", action="store_true",      help="Use internal oscillator")
-    parser.add_argument("--sdram-rate",       default="1:1",            help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate")
+    parser.add_argument("--sdram-rate",       default="1:1",            help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate")
+    builder_args(parser)
+    soc_core_args(parser)
+    trellis_args(parser)
     args = parser.parse_args()
 
     assert not (args.with_ethernet and args.with_etherbone)

litex_boards/targets/crosslink_nx_evn.py

@@ -102,11 +102,11 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Crosslink-NX Eval Board")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--load", action="store_true", help="Load bitstream")
-    parser.add_argument("--sys-clk-freq",  default=75e6, help="System clock frequency (default=75MHz)")
-    parser.add_argument("--serial",  default="serial", help="UART Pins: serial (requires R15 and R17 to be soldered) or serial_pmod[0-2] (default=serial)")
-    parser.add_argument("--prog-target",  default="direct", help="Programming Target: direct or flash")
+    parser.add_argument("--build",         action="store_true", help="Build bitstream")
+    parser.add_argument("--load",          action="store_true", help="Load bitstream")
+    parser.add_argument("--sys-clk-freq",  default=75e6,        help="System clock frequency (default: 75MHz)")
+    parser.add_argument("--serial",        default="serial",    help="UART Pins: serial (default, requires R15 and R17 to be soldered) or serial_pmod[0-2]")
+    parser.add_argument("--prog-target",   default="direct",    help="Programming Target: direct or flash")
     builder_args(parser)
     soc_core_args(parser)
     args = parser.parse_args()

litex_boards/targets/crosslink_nx_vip.py

@@ -107,11 +107,11 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Crosslink-NX VIP Board")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--load", action="store_true", help="Load bitstream")
-    parser.add_argument("--with-hyperram", default="none", help="Enable use of HyperRAM chip 0 or 1 (default=none)")
-    parser.add_argument("--sys-clk-freq",  default=75e6, help="System clock frequency (default=75MHz)")
-    parser.add_argument("--prog-target",  default="direct", help="Programming Target: direct or flash")
+    parser.add_argument("--build",         action="store_true", help="Build bitstream")
+    parser.add_argument("--load",          action="store_true", help="Load bitstream")
+    parser.add_argument("--with-hyperram", default="none",      help="Enable use of HyperRAM chip: none (default), 0 or 1")
+    parser.add_argument("--sys-clk-freq",  default=75e6,        help="System clock frequency (default: 75MHz)")
+    parser.add_argument("--prog-target",   default="direct",    help="Programming Target: direct (default) or flash")
     builder_args(parser)
     soc_core_args(parser)
     args = parser.parse_args()

litex_boards/targets/de0nano.py

@@ -96,9 +96,9 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on DE0-Nano")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--load",  action="store_true", help="Load bitstream")
-    parser.add_argument("--sdram-rate",  default="1:1", help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate")
+    parser.add_argument("--build",       action="store_true", help="Build bitstream")
+    parser.add_argument("--load",        action="store_true", help="Load bitstream")
+    parser.add_argument("--sdram-rate",  default="1:1",       help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate")
     builder_args(parser)
     soc_sdram_args(parser)
     args = parser.parse_args()

litex_boards/targets/de10lite.py

@@ -104,11 +104,11 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on DE10-Lite")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--load",  action="store_true", help="Load bitstream")
+    parser.add_argument("--build",    action="store_true", help="Build bitstream")
+    parser.add_argument("--load",     action="store_true", help="Load bitstream")
+    parser.add_argument("--with-vga", action="store_true", help="Enable VGA support")
     builder_args(parser)
     soc_sdram_args(parser)
-    parser.add_argument("--with-vga", action="store_true", help="Enable VGA support")
     args = parser.parse_args()
 
     soc = BaseSoC(with_vga=args.with_vga, **soc_sdram_argdict(args))

litex_boards/targets/de10nano.py

@@ -115,14 +115,14 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on DE10-Nano")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--load",  action="store_true", help="Load bitstream")
-    builder_args(parser)
-    soc_sdram_args(parser)
+    parser.add_argument("--build",             action="store_true", help="Build bitstream")
+    parser.add_argument("--load",              action="store_true", help="Load bitstream")
     parser.add_argument("--with-mister-sdram", action="store_true", help="Enable SDRAM with MiSTer expansion board")
     parser.add_argument("--with-mister-vga",   action="store_true", help="Enable VGA with Mister expansion board")
-    parser.add_argument("--sdram-rate",  default="1:1", help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate")
+    parser.add_argument("--sdram-rate",        default="1:1",       help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate")
     args = parser.parse_args()
+    builder_args(parser)
+    soc_sdram_args(parser)
     soc = BaseSoC(
         with_mister_sdram = args.with_mister_sdram,
         with_mister_vga   = args.with_mister_vga,

litex_boards/targets/ecp5_evn.py

@@ -68,13 +68,13 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on ECP5 Evaluation Board")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--load",  action="store_true", help="Load bitstream")
-    parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
+    parser.add_argument("--build",        action="store_true", help="Build bitstream")
+    parser.add_argument("--load",         action="store_true", help="Load bitstream")
+    parser.add_argument("--toolchain",    default="trellis",   help="FPGA toolchain: trellis (default) or diamond")
+    parser.add_argument("--sys-clk-freq", default=60e6,        help="System clock frequency (default: 60MHz)")
+    parser.add_argument("--x5-clk-freq",  type=int,            help="Use X5 oscillator as system clock at the specified frequency")
     builder_args(parser)
     soc_core_args(parser)
-    parser.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency (default=60MHz)")
-    parser.add_argument("--x5-clk-freq",  type=int,     help="Use X5 oscillator as system clock at the specified frequency")
     args = parser.parse_args()
 
     soc = BaseSoC(toolchain=args.toolchain,

litex_boards/targets/ecpix5.py

@@ -125,13 +125,13 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on ECPIX-5")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--load",  action="store_true", help="Load bitstream")
-    parser.add_argument("--with-sdcard", action="store_true",     help="Enable SDCard support")
+    parser.add_argument("--build",         action="store_true", help="Build bitstream")
+    parser.add_argument("--load",          action="store_true", help="Load bitstream")
+    parser.add_argument("--with-sdcard",   action="store_true", help="Enable SDCard support")
+    parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
     builder_args(parser)
     soc_core_args(parser)
     trellis_args(parser)
-    parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
     args = parser.parse_args()
 
     soc     = BaseSoC(with_ethernet=args.with_ethernet, **soc_core_argdict(args))

litex_boards/targets/fk33.py

@@ -101,7 +101,7 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on FK33")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
+    parser.add_argument("--build",     action="store_true", help="Build bitstream")
     parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
     parser.add_argument("--driver",    action="store_true", help="Generate PCIe driver")
     parser.add_argument("--load",      action="store_true", help="Load bitstream")

litex_boards/targets/fomu.py

@@ -148,8 +148,8 @@ def flash(bios_flash_offset):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Fomu")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--bios-flash-offset", default=0x60000, help="BIOS offset in SPI Flash")
+    parser.add_argument("--build",             action="store_true", help="Build bitstream")
+    parser.add_argument("--bios-flash-offset", default=0x60000,     help="BIOS offset in SPI Flash (default: 0x60000)")
     parser.add_argument("--flash",             action="store_true", help="Flash Bitstream")
     builder_args(parser)
     soc_core_args(parser)

litex_boards/targets/genesys2.py

@@ -97,12 +97,12 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Genesys2")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--load",  action="store_true", help="Load bitstream")
+    parser.add_argument("--build",          action="store_true", help="Build bitstream")
+    parser.add_argument("--load",           action="store_true", help="Load bitstream")
+    parser.add_argument("--with-ethernet",  action="store_true", help="Enable Ethernet support")
+    parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
     builder_args(parser)
     soc_sdram_args(parser)
-    parser.add_argument("--with-ethernet",  action="store_true", help="enable Ethernet support")
-    parser.add_argument("--with-etherbone", action="store_true", help="enable Etherbone support")
     args = parser.parse_args()
 
     assert not (args.with_ethernet and args.with_etherbone)

litex_boards/targets/hadbadge.py

@@ -86,9 +86,9 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Hackaday Badge")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
-    parser.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency (default=48MHz)")
+    parser.add_argument("--build",        action="store_true", help="Build bitstream")
+    parser.add_argument("--toolchain",    default="trellis",   help="FPGA toolchain: trellis (default) or diamond")
+    parser.add_argument("--sys-clk-freq", default=48e6,        help="System clock frequency (default: 48MHz)")
     builder_args(parser)
     soc_sdram_args(parser)
     trellis_args(parser)

litex_boards/targets/icebreaker.py

@@ -125,7 +125,7 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker")
     parser.add_argument("--build",             action="store_true", help="Build bitstream")
     parser.add_argument("--load",              action="store_true", help="Load bitstream")
-    parser.add_argument("--bios-flash-offset", default=0x40000,     help="BIOS offset in SPI Flash")
+    parser.add_argument("--bios-flash-offset", default=0x40000,     help="BIOS offset in SPI Flash (default: 0x40000)")
     parser.add_argument("--flash",             action="store_true", help="Flash Bitstream")
     builder_args(parser)
     soc_core_args(parser)

litex_boards/targets/kc705.py

@@ -132,12 +132,12 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on KC705")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--load",  action="store_true", help="Load bitstream")
-    builder_args(parser)
-    soc_sdram_args(parser)
+    parser.add_argument("--build",         action="store_true", help="Build bitstream")
+    parser.add_argument("--load",          action="store_true", help="Load bitstream")
     parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
     parser.add_argument("--with-sata",     action="store_true", help="Enable SATA support (over SFP2SATA)")
+    builder_args(parser)
+    soc_sdram_args(parser)
     args = parser.parse_args()
 
     soc = BaseSoC(with_ethernet=args.with_ethernet, with_sata=args.with_sata, **soc_sdram_argdict(args))

litex_boards/targets/linsn_rv901t.py

@@ -120,12 +120,12 @@ class EthernetSoC(BaseSoC):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Linsn RV901T")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--load",  action="store_true", help="Load bitstream")
+    parser.add_argument("--build",         action="store_true", help="Build bitstream")
+    parser.add_argument("--load",          action="store_true", help="Load bitstream")
+    parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
+    parser.add_argument("--eth-phy",       default=0, type=int, help="Ethernet PHY: 0 (default) or 1")
     builder_args(parser)
     soc_sdram_args(parser)
-    parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
-    parser.add_argument("--eth-phy",       default=0, type=int, help="Ethernet PHY 0 or 1 (default=0)")
     args = parser.parse_args()
 
     if args.with_ethernet:

litex_boards/targets/logicbone.py

@@ -159,17 +159,17 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Logicbone")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--load",  action="store_true", help="Load bitstream")
-    parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
+    parser.add_argument("--build",          action="store_true",   help="Build bitstream")
+    parser.add_argument("--load",           action="store_true",   help="Load bitstream")
+    parser.add_argument("--toolchain",      default="trellis",     help="FPGA toolchain: trellis (default) or diamond")
+    parser.add_argument("--sys-clk-freq",   default=75e6,          help="System clock frequency (default: 75MHz)")
+    parser.add_argument("--device",         default="45F",         help="FPGA device: (default: 45F)")
+    parser.add_argument("--sdram-device",   default="MT41K512M16", help="SDRAM device (default: MT41K512M16)")
+    parser.add_argument("--with-ethernet",  action="store_true",   help="Enable Ethernet support")
+    parser.add_argument("--with-sdcard",    action="store_true",   help="Enable SDCard support")
     builder_args(parser)
     soc_sdram_args(parser)
     trellis_args(parser)
-    parser.add_argument("--sys-clk-freq",   default=75e6,           help="System clock frequency (default=75MHz)")
-    parser.add_argument("--device",         default="45F",          help="ECP5 device (default=45F)")
-    parser.add_argument("--sdram-device",   default="MT41K512M16",  help="ECP5 device (default=MT41K512M16)")
-    parser.add_argument("--with-ethernet",  action="store_true",    help="enable Ethernet support")
-    parser.add_argument("--with-sdcard",    action="store_true",    help="enable SDCard support")
     args = parser.parse_args()
 
     soc = BaseSoC(

litex_boards/targets/mimas_a7.py

@@ -98,12 +98,12 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Mimas A7")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--load",  action="store_true", help="Load bitstream")
+    parser.add_argument("--build",         action="store_true", help="Build bitstream")
+    parser.add_argument("--load",          action="store_true", help="Load bitstream")
+    parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
     builder_args(parser)
     soc_sdram_args(parser)
     vivado_build_args(parser)
-    parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
     args = parser.parse_args()
 
     soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args))

litex_boards/targets/minispartan6.py

@@ -99,9 +99,9 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on MiniSpartan6")
-    parser.add_argument("--build",        action="store_true", help="Build bitstream")
-    parser.add_argument("--load",         action="store_true", help="Load bitstream")
-    parser.add_argument("--sdram-rate",  default="1:1", help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate")
+    parser.add_argument("--build",       action="store_true", help="Build bitstream")
+    parser.add_argument("--load",        action="store_true", help="Load bitstream")
+    parser.add_argument("--sdram-rate",  default="1:1",       help="SDRAM Rate: 1:1 Full Rate (default) or 1:2 Half Rate")
     builder_args(parser)
     soc_sdram_args(parser)
     args = parser.parse_args()

litex_boards/targets/mist.py

@@ -104,11 +104,11 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on MIST")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--load",  action="store_true", help="Load bitstream")
+    parser.add_argument("--build",    action="store_true", help="Build bitstream")
+    parser.add_argument("--load",     action="store_true", help="Load bitstream")
+    parser.add_argument("--with-vga", action="store_true", help="Enable VGA support")
     builder_args(parser)
     soc_sdram_args(parser)
-    parser.add_argument("--with-vga", action="store_true", help="Enable VGA support")
     args = parser.parse_args()
 
     soc = BaseSoC(with_vga=args.with_vga, **soc_sdram_argdict(args))

litex_boards/targets/netv2.py

@@ -100,11 +100,11 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on NeTV2")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--load",  action="store_true", help="Load bitstream")
+    parser.add_argument("--build",         action="store_true", help="Build bitstream")
+    parser.add_argument("--load",          action="store_true", help="Load bitstream")
+    parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
     builder_args(parser)
     soc_sdram_args(parser)
-    parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
     args = parser.parse_args()
 
     soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args))

litex_boards/targets/nexys4ddr.py

@@ -98,14 +98,14 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Nexys4DDR")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--load",  action="store_true", help="Load bitstream")
+    parser.add_argument("--build",           action="store_true", help="Build bitstream")
+    parser.add_argument("--load",            action="store_true", help="Load bitstream")
+    parser.add_argument("--sys-clk-freq",    default=75e6,        help="System clock frequency (default: 75MHz)")
+    parser.add_argument("--with-ethernet",   action="store_true", help="Enable Ethernet support")
+    parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
+    parser.add_argument("--with-sdcard",     action="store_true", help="Enable SDCard support")
     builder_args(parser)
     soc_sdram_args(parser)
-    parser.add_argument("--sys-clk-freq",  default=75e6,          help="System clock frequency (default=75MHz)")
-    parser.add_argument("--with-ethernet", action="store_true",   help="Enable Ethernet support")
-    parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
-    parser.add_argument("--with-sdcard", action="store_true",     help="Enable SDCard support")
     args = parser.parse_args()
 
     soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),

litex_boards/targets/nexys_video.py

@@ -128,14 +128,14 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Nexys Video")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--load",  action="store_true", help="Load bitstream")
-    builder_args(parser)
-    soc_sdram_args(parser)
+    parser.add_argument("--build",           action="store_true", help="Build bitstream")
+    parser.add_argument("--load",            action="store_true", help="Load bitstream")
     parser.add_argument("--with-ethernet",   action="store_true", help="Enable Ethernet support")
     parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
     parser.add_argument("--with-sdcard",     action="store_true", help="Enable SDCard support")
     parser.add_argument("--with-sata",       action="store_true", help="Enable SATA support (over FMCRAID)")
+    builder_args(parser)
+    soc_sdram_args(parser)
     args = parser.parse_args()
 
     soc = BaseSoC(with_ethernet=args.with_ethernet, with_sata=args.with_sata, **soc_sdram_argdict(args))

litex_boards/targets/orangecrab.py

@@ -32,8 +32,8 @@ from litedram.phy import ECP5DDRPHY
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq, with_usb_pll=False):
         self.rst = Signal()
-        self.clock_domains.cd_por     = ClockDomain(reset_less=True)
-        self.clock_domains.cd_sys     = ClockDomain()
+        self.clock_domains.cd_por = ClockDomain(reset_less=True)
+        self.clock_domains.cd_sys = ClockDomain()
 
         # # #
 
@@ -208,17 +208,17 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on OrangeCrab")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--load",  action="store_true", help="Load bitstream")
-    parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
+    parser.add_argument("--build",           action="store_true",  help="Build bitstream")
+    parser.add_argument("--load",            action="store_true",  help="Load bitstream")
+    parser.add_argument("--toolchain",       default="trellis",    help="FPGA  use, trellis (default) or diamond")
+    parser.add_argument("--sys-clk-freq",    default=48e6,         help="System clock frequency (default: 48MHz)")
+    parser.add_argument("--revision",        default="0.2",        help="Board Revision: 0.1 or 0.2 (default)")
+    parser.add_argument("--device",          default="25F",        help="ECP5 device (default: 25F)")
+    parser.add_argument("--sdram-device",    default="MT41K64M16", help="ECP5 device (default: MT41K64M16)")
+    parser.add_argument("--with-spi-sdcard", action="store_true",  help="Enable SPI-mode SDCard support")
     builder_args(parser)
     soc_sdram_args(parser)
     trellis_args(parser)
-    parser.add_argument("--sys-clk-freq", default=48e6,         help="System clock frequency (default=48MHz)")
-    parser.add_argument("--revision",     default="0.2",        help="Board Revision {0.1, 0.2} (default=0.2)")
-    parser.add_argument("--device",       default="25F",        help="ECP5 device (default=25F)")
-    parser.add_argument("--sdram-device", default="MT41K64M16", help="ECP5 device (default=MT41K64M16)")
-    parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
     args = parser.parse_args()
 
     soc = BaseSoC(

litex_boards/targets/pano_logic_g2.py

@@ -80,13 +80,13 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Pano Logic G2")
-    parser.add_argument("--build",    action="store_true", help="Build bitstream")
-    parser.add_argument("--load",     action="store_true", help="Load bitstream")
-    parser.add_argument("--revision", default="c",         help="Board revision c (default) or b")
-    builder_args(parser)
-    soc_core_args(parser)
+    parser.add_argument("--build",          action="store_true", help="Build bitstream")
+    parser.add_argument("--load",           action="store_true", help="Load bitstream")
+    parser.add_argument("--revision",       default="c",         help="Board revision c (default) or b")
     parser.add_argument("--with-ethernet",  action="store_true", help="Enable Ethernet support")
     parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
+    builder_args(parser)
+    soc_core_args(parser)
     args = parser.parse_args()
 
     assert not (args.with_ethernet and args.with_etherbone)

litex_boards/targets/simple.py

@@ -48,12 +48,12 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="Generic LiteX SoC")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
+    parser.add_argument("platform",                             help="Module name of the platform to build for")
+    parser.add_argument("--build",         action="store_true", help="Build bitstream")
+    parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
+    parser.add_argument("--toolchain",     default=None,        help="FPGA toolchain (None default)")
     builder_args(parser)
     soc_core_args(parser)
-    parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
-    parser.add_argument("platform",                             help="Module name of the platform to build for")
-    parser.add_argument("--toolchain", default=None,   help="FPGA gateware toolchain used for build")
     args = parser.parse_args()
 
     platform_module = importlib.import_module(args.platform)

litex_boards/targets/tec0117.py

@@ -105,8 +105,8 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker")
     parser.add_argument("--build",             action="store_true", help="Build bitstream")
     parser.add_argument("--load",              action="store_true", help="Load bitstream")
-    parser.add_argument("--bios-flash-offset", default=0,     help="BIOS offset in SPI Flash")
-    parser.add_argument("--flash",             action="store_true", help="Flash bios")
+    parser.add_argument("--bios-flash-offset", default=0x00000,     help="BIOS offset in SPI Flash (0x00000 default)")
+    parser.add_argument("--flash",             action="store_true", help="Flash BIOS")
     builder_args(parser)
     soc_core_args(parser)
     args = parser.parse_args()

litex_boards/targets/trellisboard.py

@@ -160,16 +160,16 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Trellis Board")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--load",  action="store_true", help="Load bitstream")
-    parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
+    parser.add_argument("--build",           action="store_true", help="Build bitstream")
+    parser.add_argument("--load",            action="store_true", help="Load bitstream")
+    parser.add_argument("--toolchain",       default="trellis",   help="FPGA toolchain: trellis (default) or diamond")
+    parser.add_argument("--sys-clk-freq",    default=75e6,        help="System clock frequency (default: 75MHz)")
+    parser.add_argument("--with-ethernet",   action="store_true", help="Enable Ethernet support")
+    parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
+    parser.add_argument("--with-sdcard",     action="store_true", help="Enable SDCard support")
     builder_args(parser)
     soc_sdram_args(parser)
     trellis_args(parser)
-    parser.add_argument("--sys-clk-freq",    default=75e6,        help="system clock frequency (default=75MHz)")
-    parser.add_argument("--with-ethernet",   action="store_true", help="enable Ethernet support")
-    parser.add_argument("--with-spi-sdcard", action="store_true", help="enable SPI-mode SDCard support")
-    parser.add_argument("--with-sdcard",     action="store_true", help="enable SDCard support")
     args = parser.parse_args()
 
     soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),

litex_boards/targets/ulx3s.py

@@ -129,17 +129,17 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on ULX3S")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--load",  action="store_true", help="Load bitstream")
-    parser.add_argument("--toolchain", default="trellis",   help="Gateware toolchain to use, trellis (default) or diamond")
-    parser.add_argument("--device",             dest="device",    default="LFE5U-45F", help="FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F")
-    parser.add_argument("--revision", default="2.0", type=str,  help="Board revision 2.0 (default), 1.7")
-    parser.add_argument("--sys-clk-freq", default=50e6,           help="System clock frequency (default=50MHz)")
-    parser.add_argument("--sdram-module", default="MT48LC16M16",  help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)")
-    parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
-    parser.add_argument("--with-sdcard", action="store_true",     help="Enable SDCard support")
-    parser.add_argument("--with-oled", action="store_true",     help="Enable SDD1331 OLED support")
-    parser.add_argument("--sdram-rate",  default="1:1", help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate")
+    parser.add_argument("--build",           action="store_true",   help="Build bitstream")
+    parser.add_argument("--load",            action="store_true",   help="Load bitstream")
+    parser.add_argument("--toolchain",       default="trellis",     help="FPGA toolchain: trellis (default) or diamond")
+    parser.add_argument("--device",          default="LFE5U-45F",   help="FPGA device: LFE5U-12F, LFE5U-25F, LFE5U-45F (default)  or LFE5U-85F")
+    parser.add_argument("--revision",        default="2.0",         help="Board revision: 2.0 (default) or 1.7")
+    parser.add_argument("--sys-clk-freq",    default=50e6,          help="System clock frequency  (default: 50MHz)")
+    parser.add_argument("--sdram-module",    default="MT48LC16M16", help="SDRAM module: MT48LC16M16 (default), AS4C32M16 or AS4C16M16")
+    parser.add_argument("--with-spi-sdcard", action="store_true",   help="Enable SPI-mode SDCard support")
+    parser.add_argument("--with-sdcard",     action="store_true",   help="Enable SDCard support")
+    parser.add_argument("--with-oled",       action="store_true",   help="Enable SDD1331 OLED support")
+    parser.add_argument("--sdram-rate",      default="1:1",         help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate")
     builder_args(parser)
     soc_sdram_args(parser)
     trellis_args(parser)

litex_boards/targets/versa_ecp5.py

@@ -134,17 +134,17 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Versa ECP5")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--load",  action="store_true", help="Load bitstream")
-    parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
+    parser.add_argument("--build",          action="store_true", help="Build bitstream")
+    parser.add_argument("--load",           action="store_true", help="Load bitstream")
+    parser.add_argument("--toolchain",      default="trellis",   help="FPGA toolchain: trellis (default) or diamond")
+    parser.add_argument("--sys-clk-freq",   default=75e6,        help="System clock frequency (default: 75MHz)")
+    parser.add_argument("--device",         default="LFE5UM5G",  help="FPGA device (LFE5UM5G (default) or LFE5UM)")
+    parser.add_argument("--with-ethernet",  action="store_true", help="Enable Ethernet support")
+    parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
+    parser.add_argument("--eth-phy",