diff --git a/litex_boards/targets/versa_ecp5.py b/litex_boards/targets/versa_ecp5.py
index 2cf0379dfead366f54bc902bafa0581411064338..b43bacb7082aa7fdbde9cbda3a4d6a192a8400a2 100755
--- a/litex_boards/targets/versa_ecp5.py
+++ b/litex_boards/targets/versa_ecp5.py
@@ -185,7 +185,10 @@ class BaseSoC(SoCCore):
 
         # Debug pad locator
         debug2_pads = platform.request("debug_port_2")
-        lpc_debug_mirror_clock_pad = platform.request("lpc_debug_mirror_clock")
+        try:
+            lpc_debug_mirror_clock_pad = platform.request("lpc_debug_mirror_clock")
+        except:
+            lpc_debug_mirror_clock_pad = Signal()
 
         # Host SPI Flash (Tercel core) -------------------------------------------------------------
         if with_hostspiflash: