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Kestrel Collaboration
Kestrel LiteX
litex-boards
Commits
94ccf1dd
Commit
94ccf1dd
authored
Jul 27, 2020
by
Florent Kermarrec
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targets/trellisboard: simplify clocking when no DDR3, remove firmware_ram (was here for debug).
parent
ecdc1ef7
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1
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26 additions
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3 deletions
+26
-3
litex_boards/targets/trellisboard.py
litex_boards/targets/trellisboard.py
+26
-3
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litex_boards/targets/trellisboard.py
View file @
94ccf1dd
...
...
@@ -27,6 +27,30 @@ from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
# CRG ----------------------------------------------------------------------------------------------
class
_CRG
(
Module
):
def
__init__
(
self
,
platform
,
sys_clk_freq
):
self
.
clock_domains
.
cd_por
=
ClockDomain
(
reset_less
=
True
)
self
.
clock_domains
.
cd_sys
=
ClockDomain
()
# # #
# Clk / Rst
clk12
=
platform
.
request
(
"clk12"
)
rst
=
platform
.
request
(
"user_btn"
,
0
)
# Power on reset
por_count
=
Signal
(
16
,
reset
=
2
**
16
-
1
)
por_done
=
Signal
()
self
.
comb
+=
self
.
cd_por
.
clk
.
eq
(
clk12
)
self
.
comb
+=
por_done
.
eq
(
por_count
==
0
)
self
.
sync
.
por
+=
If
(
~
por_done
,
por_count
.
eq
(
por_count
-
1
))
# PLL
self
.
submodules
.
pll
=
pll
=
ECP5PLL
()
pll
.
register_clkin
(
clk12
,
12e6
)
pll
.
create_clkout
(
self
.
cd_sys
,
sys_clk_freq
)
self
.
specials
+=
AsyncResetSynchronizer
(
self
.
cd_sys
,
~
por_done
|
~
pll
.
locked
|
rst
)
class
_CRGSDRAM
(
Module
):
def
__init__
(
self
,
platform
,
sys_clk_freq
):
self
.
clock_domains
.
cd_init
=
ClockDomain
()
self
.
clock_domains
.
cd_por
=
ClockDomain
(
reset_less
=
True
)
...
...
@@ -92,7 +116,8 @@ class BaseSoC(SoCCore):
**
kwargs
)
# CRG --------------------------------------------------------------------------------------
self
.
submodules
.
crg
=
_CRG
(
platform
,
sys_clk_freq
)
crg_cls
=
_CRGSDRAM
if
not
self
.
integrated_main_ram_size
else
_CRG
self
.
submodules
.
crg
=
crg_cls
(
platform
,
sys_clk_freq
)
# DDR3 SDRAM -------------------------------------------------------------------------------
if
not
self
.
integrated_main_ram_size
:
...
...
@@ -126,8 +151,6 @@ class BaseSoC(SoCCore):
sys_clk_freq
=
sys_clk_freq
)
self
.
add_csr
(
"leds"
)
self
.
add_ram
(
"firmware_ram"
,
0x20000000
,
0x10000
)
# Build --------------------------------------------------------------------------------------------
def
main
():
...
...
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