Update build command in README to correspond with recent LiteX changes

parent 32cd90f9
......@@ -32,7 +32,7 @@ Building the Kestrel BMC for the ECP-5 FPGA on the Versa board is quite straight
Please see the [Quick Start Guide](https://gitlab.raptorengineering.com/kestrel-collaboration/kestrel-litex/litex/-/wikis/Quick-Start) for setup instructions applicable to the standard Raptor development environment on POWER9. After the subrepositories are set up, simply run:
cd kestrel/litex/litex-boards/litex_boards/targets
./versa_ecp5.py --device=LFE5UM --cpu-type=microwatt --cpu-variant=standard+ghdl --build --nextpnr-seed 1
./versa_ecp5.py --device=LFE5UM --cpu-type=microwatt --cpu-variant=standard+ghdl+irq --with-ethernet --build --nextpnr-seed 1
# Updating the bitstream with new firmware
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