Add RCS Sparrowhawk and Arctic Tern platforms

Sparrowhawk is a single CPU POWER9 OpenVPX platform
Arctic Tern is a ModBMC-based platform for BMC development

README.md

@@ -33,6 +33,10 @@ Please see the [Quick Start Guide](https://gitlab.raptorengineering.com/kestrel-
 
     cd kestrel/litex/litex-boards/litex_boards/targets
     ./kestrel_versa_ecp5.py --device=LFE5UM --cpu-type=microwatt --cpu-variant=standard+ghdl+irq --with-ethernet --build --nextpnr-seed 1
+    or
+    ./sparrowhawk_bmc.py --device=LFE5UM5G --cpu-type=microwatt --cpu-variant=standard+ghdl+irq --with-ethernet --with-video --build --nextpnr-seed 1
+    or
+    ./rcs_arctic_tern_bmc_card.py --device=LFE5UM --cpu-type=microwatt --cpu-variant=standard+ghdl+irq --with-ethernet --with-video --build --nextpnr-seed 1
 
 # Updating the bitstream with new firmware
 

litex_boards/platforms/rcs_arctic_tern_bmc_card.py

+#
+# This file is part of LiteX-Boards.
+#
+# Copyright (c) 2022 Raptor Engineering, LLC
+# SPDX-License-Identifier: BSD-2-Clause
+
+from litex.build.generic_platform import *
+from litex.build.lattice import LatticePlatform
+from litex.build.lattice.programmer import OpenOCDJTAGProgrammer
+
+import os
+
+# IOs ----------------------------------------------------------------------------------------------
+
+_io = [
+    # Clk / Rst (module)
+    ("clk125",       0, Pins("B6"), IOStandard("LVCMOS33")),
+    ("rst_n",        0, Pins("T3"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+
+    # BMC serial (module)
+    ("serial", 0,
+        Subsignal("rx", Pins("B8"), IOStandard("LVCMOS33")),
+        Subsignal("tx", Pins("A7"), IOStandard("LVCMOS33")),
+    ),
+
+    # Host serial (module)
+    ("serial", 1,
+        Subsignal("rx", Pins("C1"), IOStandard("LVCMOS33")),
+        Subsignal("tx", Pins("C2"), IOStandard("LVCMOS33")),
+        Subsignal("rts", Pins("C8"), IOStandard("LVCMOS33")),
+        Subsignal("cts", Pins("D8"), IOStandard("LVCMOS33")),
+    ),
+
+    # DDR3 SDRAM (module)
+    ("ddram", 0,
+        Subsignal("a", Pins(
+            "J1 K1 G2 H2 F1 G1 J4 J3 J5 K3 K2 H1 M5 K4 L4"),
+            IOStandard("SSTL135_I")),
+        Subsignal("ba",    Pins("K5 L5 M1"), IOStandard("SSTL135_I")),
+        Subsignal("ras_n", Pins("L2"), IOStandard("SSTL135_I")),
+        Subsignal("cas_n", Pins("N2"), IOStandard("SSTL135_I")),
+        Subsignal("we_n",  Pins("N1"), IOStandard("SSTL135_I")),
+        Subsignal("cs_n",  Pins("P5"), IOStandard("SSTL135_I")),
+        Subsignal("dm", Pins("R20 N18 F20 E18"), IOStandard("SSTL135_I")),
+        Subsignal("dq", Pins(
+            "T20 U17 T18 U16 U19 T17 U20 U18",
+            "L19 M18 L17 L16 L20 M19 L18 M20",
+            "J20 K18 F19 K19 J19 J18 G20 K20",
+            "G16 H18 H16 F18 J16 E17 J17 H17"),
+            IOStandard("SSTL135_I"),
+            Misc("TERMINATION=75")),
+        Subsignal("dqs_p", Pins("T19 N16 G19 F17"), IOStandard("SSTL135D_I"),
+            Misc("TERMINATION=OFF"),
+            Misc("DIFFRESISTOR=100")),
+        Subsignal("clk_p", Pins("P19 E16"), IOStandard("SSTL135D_I")),
+        Subsignal("cke",   Pins("N5"), IOStandard("SSTL135_I")),
+        Subsignal("odt",   Pins("M3"), IOStandard("SSTL135_I")),
+        Subsignal("reset_n", Pins("L1"), IOStandard("SSTL135_I")),
+        Misc("SLEWRATE=FAST"),
+    ),
+
+    # PCIe (module)
+    ("pcie_x1", 0,
+        Subsignal("clk_p", Pins("Y11")),
+        Subsignal("clk_n", Pins("Y12")),
+        Subsignal("rx_p",  Pins("Y5")),
+        Subsignal("rx_n",  Pins("Y6")),
+        Subsignal("tx_p",  Pins("W4")),
+        Subsignal("tx_n",  Pins("W5")),
+        Subsignal("perst", Pins("A6"), IOStandard("LVCMOS33")),
+    ),
+
+    # Inter-module SERDES (module)
+    ("serdes_x2", 0,
+        Subsignal("clk_p", Pins("Y19")),
+        Subsignal("clk_n", Pins("W20")),
+        Subsignal("rx_p",  Pins("Y14 Y16")),
+        Subsignal("rx_n",  Pins("Y15 Y17")),
+        Subsignal("tx_p",  Pins("W13 W17")),
+        Subsignal("tx_n",  Pins("W14 W18")),
+        Subsignal("perst", Pins("A6"), IOStandard("LVCMOS33")),
+    ),
+
+    # Bitstream Flash device (module)
+    # Contains FPGA bistream, USRMCLK block required for clock output
+    ("fpgaspiflash4x", 0,
+        Subsignal("cs_n", Pins("R2")),
+        Subsignal("dq",   Pins("W2 V2 Y2 W1")),
+        IOStandard("LVCMOS33"),
+        Misc("SLEWRATE=SLOW"),
+        Misc("DRIVE=16"),
+    ),
+
+    # BMC firmware Flash device (carrier card)
+    ("bmcspiflash4x", 0,
+        Subsignal("cs_n", Pins("G5")),
+        Subsignal("clk",  Pins("E5")),
+        Subsignal("dq",   Pins("E3 F5 D2 H4")),
+        IOStandard("LVCMOS33"),
+        Misc("SLEWRATE=SLOW"),
+        Misc("DRIVE=16"),
+    ),
+
+    # Host Flash device (carrier card)
+    ("hostspiflash4x", 0,
+        Subsignal("cs_n", Pins("E2")),
+        Subsignal("clk",  Pins("G3")),
+        Subsignal("dq",   Pins("F2 F3 D1 A2")),
+        IOStandard("LVCMOS33"),
+        Misc("SLEWRATE=SLOW"),
+        Misc("DRIVE=16"),
+    ),
+
+    # I2C bus 1
+    # 3-pin header (carrier card)
+    ("i2c_master", 0,
+        Subsignal("sda",       Pins("E4"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+        Subsignal("scl",       Pins("D5"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+    ),
+
+    # I2C bus 2
+    # 3-pin header (carrier card)
+    ("i2c_master", 1,
+        Subsignal("sda",       Pins("B1"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+        Subsignal("scl",       Pins("B2"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+    ),
+
+    # I2C bus 3
+    # 3-pin header (carrier card)
+    ("i2c_master", 2,
+        Subsignal("sda",       Pins("C7"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+        Subsignal("scl",       Pins("E8"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+    ),
+
+    # I2C bus 4
+    # GPIO expander 1 (module)
+    ("i2c_master", 3,
+        Subsignal("sda",       Pins("U1"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+        Subsignal("scl",       Pins("R1"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+    ),
+
+    # I2C bus 5
+    # GPIO expander 2 (module)
+    ("i2c_master", 4,
+        Subsignal("sda",       Pins("A12"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+        Subsignal("scl",       Pins("E12"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+    ),
+
+    # I2C bus 9
+    ("i2c_master", 5,
+        Subsignal("sda",       Pins("R3"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+        Subsignal("scl",       Pins("U2"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+    ),
+
+    # I2C bus 12
+    # RTC + digital video + temperature sensor (module)
+    # Clock generator + PMBus (carrier card)
+    ("i2c_master", 6,
+        Subsignal("sda",       Pins("V1"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+        Subsignal("scl",       Pins("T1"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+    ),
+
+    # Host LPC interface (module)
+    ("hostlpcslave", 0,
+        Subsignal("frame_n",   Pins("D3"), Misc("PULLMODE=UP")),
+        Subsignal("reset_n",   Pins("C3"), Misc("PULLMODE=UP")),
+        Subsignal("addrdata",  Pins("C4 A3 B4 B3"), Misc("PULLMODE=UP")),
+        Subsignal("serirq",    Pins("F4"), Misc("PULLMODE=UP")),
+        Subsignal("clk",       Pins("H5"), Misc("PULLMODE=NONE")),
+        IOStandard("LVCMOS33"),
+        Misc("SLEWRATE=SLOW"),
+        Misc("DRIVE=16"),
+    ),
+
+    # FSI (carrier card)
+    ("openfsi_master", 0,
+        Subsignal("clock",          Pins("A18"), IOStandard("LVCMOS33")),
+        Subsignal("data",           Pins("B18"), IOStandard("LVCMOS33")),
+        Subsignal("data_direction", Pins("T2"), IOStandard("LVCMOS33")),
+    ),
+
+    # RGMII Ethernet (module)
+    ("eth_clocks", 0,
+        Subsignal("tx", Pins("C11")),
+        Subsignal("rx", Pins("A9")),
+        IOStandard("LVCMOS33")
+    ),
+    ("eth", 0,
+        # Reset is available on GPIO expander 2
+        Subsignal("mdio",    Pins("D9")),
+        Subsignal("mdc",     Pins("E6")),
+        Subsignal("rx_ctl",  Pins("A8")),
+        Subsignal("rx_data", Pins("E9 C9 D10 E10")),
+        Subsignal("tx_ctl",  Pins("C10")),
+        Subsignal("tx_data", Pins("B10 A10 B11 A11")),
+        IOStandard("LVCMOS33")
+    ),
+
+    # Digital video (module)
+    ("dvo", 0,
+        Subsignal("r", Pins(
+            "C14 E14 D14 E13 D13 C13 E11 C12")),
+        Subsignal("g", Pins(
+            "B19 B20 C17 C16 C15 D16 D15 E15")),
+        Subsignal("b", Pins(
+            "A14 A15 B15 A16 B16 A17 A19 B17")),
+        Subsignal("de",      Pins("A13")),
+        Subsignal("hsync_n", Pins("B13")),
+        Subsignal("vsync_n", Pins("B12")),
+        Subsignal("clk",     Pins("D11")),
+        IOStandard("LVCMOS33")
+    ),
+
+    # 4-pin fan headers (carrier card)
+    ("pwm_tach_pads", 0,
+        Subsignal("pwm1", Pins("B5"), IOStandard("LVCMOS33")),
+        Subsignal("pwm2", Pins("C5"), IOStandard("LVCMOS33")),
+        Subsignal("pwm3", Pins("E1"), IOStandard("LVCMOS33")),
+        Subsignal("pwm4", Pins("H3"), IOStandard("LVCMOS33")),
+        Subsignal("tach1", Pins("D7"), IOStandard("LVCMOS33")),
+        Subsignal("tach2", Pins("C6"), IOStandard("LVCMOS33")),
+        Subsignal("tach3", Pins("E7"), IOStandard("LVCMOS33")),
+        Subsignal("tach4", Pins("D6"), IOStandard("LVCMOS33")),
+    ),
+]
+
+# Platform -----------------------------------------------------------------------------------------
+
+class Platform(LatticePlatform):
+    default_clk_name   = "clk125"
+    default_clk_period = 1e9/125e6
+
+    def __init__(self, device="LFE5UM", speed_grade="7", toolchain="trellis", **kwargs):
+        assert device in ["LFE5UM5G", "LFE5UM"]
+        if device is "LFE5UM5G":
+            speed_grade = "8"
+        LatticePlatform.__init__(self, device + "-85F-" + speed_grade + "CABGA381", _io, toolchain=toolchain, **kwargs)
+
+    def request(self, *args, **kwargs):
+        return LatticePlatform.request(self, *args, **kwargs)
+
+    def create_programmer(self):
+        return OpenOCDJTAGProgrammer("openocd_evn_ecp5.cfg")
+
+    def do_finalize(self, fragment):
+        LatticePlatform.do_finalize(self, fragment)
+        self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6)
+        self.add_period_constraint(self.lookup_request("eth_clocks:rx", 0, loose=True), 1e9/125e6)

litex_boards/platforms/sparrowhawk_bmc.py

+#
+# This file is part of LiteX-Boards.
+#
+# Copyright (c) 2017 Sergiusz Bazanski <q3k@q3k.org>
+# Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
+# Copyright (c) 2020-2021 Raptor Engineering, LLC
+# SPDX-License-Identifier: BSD-2-Clause
+
+from litex.build.generic_platform import *
+from litex.build.lattice import LatticePlatform
+from litex.build.lattice.programmer import OpenOCDJTAGProgrammer
+
+# IOs ----------------------------------------------------------------------------------------------
+
+_io = [
+    # Clk / Rst
+    ("clk24", 0, Pins("B6"), IOStandard("LVCMOS33")),
+    ("rst_n",  0, Pins("T2"), IOStandard("LVCMOS33")),	# Front panel power button, for easy debugging
+
+    # GPIO Bank 1
+    # BMC_POWER_UP | BMC_BOOT_PHASE | BP_SYSRESET_N | DBG_FSI0_EN | SYS_PWROK_BUF | BMC_INTRUDER_N | PM_CP0_ATTENTION_B | BMC_FP_ID_BTN
+    ("gpio1", 0, Pins("T17 U16 C5 C6 T1 V1 R3 U2"), IOStandard("LVCMOS33")),
+
+    # Serial (BMC COM1)
+    ("serial", 0,
+        Subsignal("rx", Pins("D10"), IOStandard("LVCMOS33")),
+        Subsignal("tx", Pins("E10"), IOStandard("LVCMOS33")),
+    ),
+
+    # NCSI Ethernet
+    ("eth_clocks", 0,
+        Subsignal("ref_clk", Pins("A9")),
+        IOStandard("LVCMOS33")
+    ),
+    ("eth", 0,
+        Subsignal("crs_dv",  Pins("B9")),
+        Subsignal("rx_data", Pins("A10 B10")),
+        Subsignal("tx_en",   Pins("B11")),
+        Subsignal("tx_data", Pins("C11 A11")),
+        IOStandard("LVCMOS33")
+    ),
+
+    # PCIe
+    ("pcie_x1", 0,
+        Subsignal("clk_p", Pins("Y11")),
+        Subsignal("clk_n", Pins("Y12")),
+        Subsignal("rx_p",  Pins("Y5")),
+        Subsignal("rx_n",  Pins("Y6")),
+        Subsignal("tx_p",  Pins("W4")),
+        Subsignal("tx_n",  Pins("W5")),
+        Subsignal("perst", Pins("A6"), IOStandard("LVCMOS33")),
+    ),
+
+    # I2C
+    # Regulators
+    ("i2c_master", 1,
+        Subsignal("sda",            Pins("B8"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+        Subsignal("scl",            Pins("A7"),  IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+    ),
+
+    # SEEPROM
+    ("i2c_master", 2,
+        Subsignal("sda",            Pins("D9"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+        Subsignal("scl",            Pins("A8"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+    ),
+
+    # CPU clock
+    ("i2c_master", 3,
+        Subsignal("sda",            Pins("U1"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+        Subsignal("scl",            Pins("R1"),  IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+    ),
+
+    # Platform control FPGA / temperature sensors
+    ("i2c_master", 4,
+        Subsignal("sda",            Pins("C7"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+        Subsignal("scl",            Pins("E8"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+    ),
+
+    # RTC
+    ("i2c_master", 5,
+        Subsignal("sda",            Pins("C8"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+        Subsignal("scl",            Pins("D8"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+    ),
+
+    # Digital Video
+    ("i2c_master", 6,
+        Subsignal("sda",            Pins("L17"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+        Subsignal("scl",            Pins("L18"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
+    ),
+
+    # FSI
+    ("openfsi_master", 0,
+        Subsignal("clock",          Pins("E7"), IOStandard("LVCMOS33")),
+        Subsignal("data",           Pins("D6"), IOStandard("LVCMOS33")),
+        Subsignal("data_direction", Pins("D7"), IOStandard("LVCMOS33")),
+    ),
+
+    # ECP5 Flash device
+    # Also contains FPGA bistream, USRMCLK block required for clock output
+    ("bmcspiflash4x", 0,
+        Subsignal("cs_n", Pins("R2")),
+        Subsignal("dq",   Pins("W2 V2 Y2 W1")),
+        IOStandard("LVCMOS33"),
+        Misc("SLEWRATE=SLOW"),
+        Misc("DRIVE=16"),
+    ),
+
+    # Host Flash device
+    ("hostspiflash4x", 0,
+        Subsignal("cs_n", Pins("E2")),
+        Subsignal("clk",  Pins("G3")),
+        Subsignal("dq",   Pins("F2 F3 B5 B2")),
+        IOStandard("LVCMOS33"),
+        Misc("SLEWRATE=SLOW"),
+        Misc("DRIVE=16"),
+    ),
+
+    # Host LPC interface
+    ("hostlpcslave", 0,
+        Subsignal("frame_n",   Pins("D3"), Misc("PULLMODE=UP")),
+        Subsignal("reset_n",   Pins("C3"), Misc("PULLMODE=UP")),
+        Subsignal("addrdata",  Pins("C4 A3 B4 B3"), Misc("PULLMODE=UP")),
+        Subsignal("serirq",    Pins("F4"), Misc("PULLMODE=UP")),
+        Subsignal("clk",       Pins("H5"), Misc("PULLMODE=NONE")),
+        IOStandard("LVCMOS33"),
+        Misc("SLEWRATE=SLOW"),
+        Misc("DRIVE=16"),
+    ),
+    ("hostlpcsecureinterface", 0,
+        Subsignal("clk_out",   Pins("H3"), Misc("PULLMODE=UP")),
+        IOStandard("LVCMOS33"),
+        Misc("SLEWRATE=FAST"),
+        Misc("DRIVE=16"),
+    ),
+
+    # Digital video
+    ("dvo", 0,
+        Subsignal("r", Pins(
+            "R16 P16 N17 P17 N18 M17 N16 M18")),
+        Subsignal("g", Pins(
+            "T20 R20 P20 P18 P19 N20 N19 R17")),
+        Subsignal("b", Pins(
+            "T16 R18 T19 U17 U18 T18 U19 U20")),
+        Subsignal("de",      Pins("M19")),
+        Subsignal("hsync_n", Pins("L19")),
+        Subsignal("vsync_n", Pins("M20")),
+        Subsignal("clk",     Pins("L20")),
+        IOStandard("LVCMOS33")
+    ),
+]
+
+# Connectors ---------------------------------------------------------------------------------------
+
+_connectors = [
+]
+
+# Platform -----------------------------------------------------------------------------------------
+
+class Platform(LatticePlatform):
+    default_clk_name   = "clk24"
+    default_clk_period = 1e9/24e6
+
+    def __init__(self, device="LFE5UM5G", toolchain="trellis", **kwargs):
+        assert device in ["LFE5UM5G", "LFE5UM"]
+        LatticePlatform.__init__(self, device + "-85F-8BG381C", _io, _connectors, toolchain=toolchain, **kwargs)
+
+    def create_programmer(self):
+        return OpenOCDJTAGProgrammer("openocd_sparrowhawk_bmc.cfg")
+
+    def do_finalize(self, fragment):
+        self.add_period_constraint(self.lookup_request("clk24", loose=True), 1e9/24e6)
+        self.add_period_constraint(self.lookup_request("eth_clocks:ref_clk", 0, loose=True), 1e9/50e6)