Merge pull request #116 from litex-hub/litedram_write_latency

targets/s7/us: update sdram (manual cmd_latency no longer needed).

litex_boards/targets/alveo_u250.py

@@ -78,7 +78,6 @@ class BaseSoC(SoCCore):
                 memtype          = "DDR4",
                 sys_clk_freq     = sys_clk_freq,
                 iodelay_clk_freq = 500e6,
-                cmd_latency      = 1,
                 is_rdimm         = True)
             self.add_csr("ddrphy")
             self.add_sdram("sdram",

litex_boards/targets/genesys2.py

@@ -63,8 +63,7 @@ class BaseSoC(SoCCore):
             self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
                 memtype      = "DDR3",
                 nphases      = 4,
-                sys_clk_freq = sys_clk_freq,
-                cmd_latency  = 1)
+                sys_clk_freq = sys_clk_freq)
             self.add_csr("ddrphy")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,

litex_boards/targets/kc705.py

@@ -65,8 +65,7 @@ class BaseSoC(SoCCore):
             self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
                 memtype      = "DDR3",
                 nphases      = 4,
-                sys_clk_freq = sys_clk_freq,
-                cmd_latency  = 1)
+                sys_clk_freq = sys_clk_freq)
             self.add_csr("ddrphy")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,

litex_boards/targets/kcu105.py

@@ -74,8 +74,7 @@ class BaseSoC(SoCCore):
             self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"),
                 memtype          = "DDR4",
                 sys_clk_freq     = sys_clk_freq,
-                iodelay_clk_freq = 200e6,
-                cmd_latency      = 1)
+                iodelay_clk_freq = 200e6)
             self.add_csr("ddrphy")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,

litex_boards/targets/kx2.py

@@ -62,8 +62,7 @@ class BaseSoC(SoCCore):
             self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
                 memtype      = "DDR3",
                 nphases      = 4,
-                sys_clk_freq = sys_clk_freq,
-                cmd_latency  = 1)
+                sys_clk_freq = sys_clk_freq)
             self.add_csr("ddrphy")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,

litex_boards/targets/mercury_xu5.py

@@ -71,8 +71,7 @@ class BaseSoC(SoCCore):
             self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"),
                 memtype          = "DDR4",
                 sys_clk_freq     = sys_clk_freq,
-                iodelay_clk_freq = 500e6,
-                cmd_latency      = 1)
+                iodelay_clk_freq = 500e6)
             self.add_csr("ddrphy")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,

litex_boards/targets/vc707.py

@@ -60,8 +60,7 @@ class BaseSoC(SoCCore):
             self.submodules.ddrphy = s7ddrphy.V7DDRPHY(platform.request("ddram"),
                 memtype      = "DDR3",
                 nphases      = 4,
-                sys_clk_freq = sys_clk_freq,
-                cmd_latency  = 1)
+                sys_clk_freq = sys_clk_freq)
             self.add_csr("ddrphy")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,

litex_boards/targets/vcu118.py

@@ -71,8 +71,7 @@ class BaseSoC(SoCCore):
             self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"),
                 memtype          = "DDR4",
                 sys_clk_freq     = sys_clk_freq,
-                iodelay_clk_freq = 500e6,
-                cmd_latency      = 1)
+                iodelay_clk_freq = 500e6)
             self.add_csr("ddrphy")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,

litex_boards/targets/xcu1525.py

@@ -76,8 +76,7 @@ class BaseSoC(SoCCore):
                 pads             = platform.request("ddram", ddram_channel),
                 memtype          = "DDR4",
                 sys_clk_freq     = sys_clk_freq,
-                iodelay_clk_freq = 500e6,
-                cmd_latency      = 1)
+                iodelay_clk_freq = 500e6)
             self.add_csr("ddrphy")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,

litex_boards/targets/zcu104.py

@@ -71,8 +71,7 @@ class BaseSoC(SoCCore):
             self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"),
                 memtype          = "DDR4",
                 sys_clk_freq     = sys_clk_freq,
-                iodelay_clk_freq = 500e6,
-                cmd_latency      = 1)
+                iodelay_clk_freq = 500e6)
             self.add_csr("ddrphy")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,