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Kestrel Collaboration
Kestrel LiteX
litex-boards
Commits
8a3b453e
Commit
8a3b453e
authored
Jul 23, 2020
by
Florent Kermarrec
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add Zybo Z7 minimal platform/targets: no PS7 support and USB-UART PMOD on JB.
parent
e723bef4
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litex_boards/platforms/zybo_z7.py
litex_boards/platforms/zybo_z7.py
+74
-0
litex_boards/targets/zybo_z7.py
litex_boards/targets/zybo_z7.py
+73
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litex_boards/platforms/zybo_z7.py
0 → 100644
View file @
8a3b453e
# This file is Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
from
litex.build.generic_platform
import
*
from
litex.build.xilinx
import
XilinxPlatform
,
VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io
=
[
# clk125
(
"clk125"
,
0
,
Pins
(
"L16"
),
IOStandard
(
"LVCMOS33"
)),
# user led
(
"user_led"
,
0
,
Pins
(
"M14"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_led"
,
1
,
Pins
(
"M15"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_led"
,
2
,
Pins
(
"G14"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_led"
,
3
,
Pins
(
"D18"
),
IOStandard
(
"LVCMOS33"
)),
# user sw
(
"user_sw"
,
0
,
Pins
(
"G15"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_sw"
,
1
,
Pins
(
"P15"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_sw"
,
2
,
Pins
(
"W13"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_sw"
,
3
,
Pins
(
"T16"
),
IOStandard
(
"LVCMOS33"
)),
# user btn
(
"user_btn"
,
0
,
Pins
(
"R18"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_btn"
,
1
,
Pins
(
"P16"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_btn"
,
2
,
Pins
(
"V16"
),
IOStandard
(
"LVCMOS33"
)),
(
"user_btn"
,
3
,
Pins
(
"Y16"
),
IOStandard
(
"LVCMOS33"
)),
# serial
(
"serial"
,
0
,
Subsignal
(
"tx"
,
Pins
(
"T17"
)),
Subsignal
(
"rx"
,
Pins
(
"Y17"
)),
IOStandard
(
"LVCMOS33"
)
),
]
_usb_uart_pmod_io
=
[
# USB-UART PMOD on JB:
# - https://store.digilentinc.com/pmod-usbuart-usb-to-uart-interface/
(
"usb_uart"
,
0
,
Subsignal
(
"tx"
,
Pins
(
"pmodb:1"
)),
Subsignal
(
"rx"
,
Pins
(
"pmodb:2"
)),
IOStandard
(
"LVCMOS33"
)
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors
=
[
(
"pmoda"
,
"N15 L14 K16 K14 N16 L15 J16 J14"
),
# XADC
(
"pmodb"
,
"T20 U20 V20 W20 Y18 Y19 W18 W19"
),
(
"pmodc"
,
"V15 W15 T11 T10 W14 Y14 T12 U12"
),
(
"pmodd"
,
"T14 T15 P14 R14 U14 U15 V17 V18"
),
(
"pmode"
,
"V12 W16 J15 H15 V13 U17 T17 Y17"
),
]
# Platform -----------------------------------------------------------------------------------------
class
Platform
(
XilinxPlatform
):
default_clk_name
=
"clk128"
default_clk_period
=
1e9
/
125e6
def
__init__
(
self
):
XilinxPlatform
.
__init__
(
self
,
"xc7z010-clg400-1"
,
_io
,
_connectors
,
toolchain
=
"vivado"
)
self
.
add_extension
(
_usb_uart_pmod_io
)
def
create_programmer
(
self
):
return
VivadoProgrammer
()
def
do_finalize
(
self
,
fragment
):
XilinxPlatform
.
do_finalize
(
self
,
fragment
)
self
.
add_period_constraint
(
self
.
lookup_request
(
"clk125"
,
loose
=
True
),
1e9
/
125e6
)
litex_boards/targets/zybo_z7.py
0 → 100755
View file @
8a3b453e
#!/usr/bin/env python3
# This file is Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>,
# License: BSD
import
os
import
argparse
from
migen
import
*
from
litex_boards.platforms
import
zybo_z7
from
litex.build.xilinx.vivado
import
vivado_build_args
,
vivado_build_argdict
from
litex.soc.cores.clock
import
*
from
litex.soc.integration.soc_core
import
*
from
litex.soc.integration.builder
import
*
from
litex.soc.cores.led
import
LedChaser
# CRG ----------------------------------------------------------------------------------------------
class
_CRG
(
Module
):
def
__init__
(
self
,
platform
,
sys_clk_freq
):
self
.
clock_domains
.
cd_sys
=
ClockDomain
()
# # #
self
.
submodules
.
pll
=
pll
=
S7PLL
(
speedgrade
=-
1
)
pll
.
register_clkin
(
platform
.
request
(
"clk125"
),
125e6
)
pll
.
create_clkout
(
self
.
cd_sys
,
sys_clk_freq
)
# BaseSoC ------------------------------------------------------------------------------------------
class
BaseSoC
(
SoCCore
):
def
__init__
(
self
,
sys_clk_freq
=
int
(
100e6
),
**
kwargs
):
platform
=
zybo_z7
.
Platform
()
# SoCCore ----------------------------------------------------------------------------------
if
kwargs
[
"uart_name"
]
==
"serial"
:
kwargs
[
"uart_name"
]
=
"usb_uart"
# Use USB-UART Pmod on JB.
SoCCore
.
__init__
(
self
,
platform
,
sys_clk_freq
,
ident
=
"LiteX SoC on Zybo Z7"
,
ident_version
=
True
,
**
kwargs
)
# CRG --------------------------------------------------------------------------------------
self
.
submodules
.
crg
=
_CRG
(
platform
,
sys_clk_freq
)
# Leds -------------------------------------------------------------------------------------
self
.
submodules
.
leds
=
LedChaser
(
pads
=
Cat
(
*
[
platform
.
request
(
"user_led"
,
i
)
for
i
in
range
(
4
)]),
sys_clk_freq
=
sys_clk_freq
)
self
.
add_csr
(
"leds"
)
# Build --------------------------------------------------------------------------------------------
def
main
():
parser
=
argparse
.
ArgumentParser
(
description
=
"LiteX SoC on Zybo Z7"
)
parser
.
add_argument
(
"--build"
,
action
=
"store_true"
,
help
=
"Build bitstream"
)
parser
.
add_argument
(
"--load"
,
action
=
"store_true"
,
help
=
"Load bitstream"
)
builder_args
(
parser
)
soc_core_args
(
parser
)
vivado_build_args
(
parser
)
args
=
parser
.
parse_args
()
soc
=
BaseSoC
(
**
soc_core_argdict
(
args
))
builder
=
Builder
(
soc
,
**
builder_argdict
(
args
))
builder
.
build
(
**
vivado_build_argdict
(
args
),
run
=
args
.
build
)
if
args
.
load
:
prog
=
soc
.
platform
.
create_programmer
()
prog
.
load_bitstream
(
os
.
path
.
join
(
builder
.
gateware_dir
,
soc
.
build_name
+
".bit"
),
device
=
1
)
if
__name__
==
"__main__"
:
main
()
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