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Kestrel Collaboration
Kestrel LiteX
litex-boards
Commits
89c5bf43
Unverified
Commit
89c5bf43
authored
Jul 24, 2020
by
enjoy-digital
Committed by
GitHub
Jul 24, 2020
Browse files
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Merge pull request #92 from rob-ng15/master
Enable use of HalfRateGENSDRPHY on de10nano
parents
1e1589a5
7cda1432
Changes
2
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Showing
2 changed files
with
54 additions
and
26 deletions
+54
-26
litex_boards/platforms/de10nano.py
litex_boards/platforms/de10nano.py
+29
-17
litex_boards/targets/de10nano.py
litex_boards/targets/de10nano.py
+25
-9
No files found.
litex_boards/platforms/de10nano.py
View file @
89c5bf43
...
...
@@ -30,13 +30,15 @@ _io = [
(
"user_sw"
,
3
,
Pins
(
"W20"
),
IOStandard
(
"3.3-V LVTTL"
)),
(
"serial"
,
0
,
Subsignal
(
"tx"
,
Pins
(
"AH9"
),
IOStandard
(
"3.3-V LVTTL"
)),
# User I/O port on Mister
Subsignal
(
"rx"
,
Pins
(
"AG11"
),
IOStandard
(
"3.3-V LVTTL"
))
# User I/O port on Mister
Subsignal
(
"tx"
,
Pins
(
"AH9"
)),
# User I/O port on Mister
Subsignal
(
"rx"
,
Pins
(
"AG11"
)),
# User I/O port on Mister
IOStandard
(
"3.3-V LVTTL"
),
Misc
(
"WEAK_PULL_UP_RESISTOR ON"
),
Misc
(
"CURRENT_STRENGTH_NEW
\
"
MAXIMUM CURRENT
\
"
"
)
),
(
"serial"
,
1
,
Subsignal
(
"tx"
,
Pins
(
"AF13"
),
IOStandard
(
"3.3-V LVTTL"
)),
# Arduino_IO1
Subsignal
(
"rx"
,
Pins
(
"AG13"
),
IOStandard
(
"3.3-V LVTTL"
))
# Arduino_IO0
Subsignal
(
"tx"
,
Pins
(
"AF13"
)),
# Arduino_IO1
Subsignal
(
"rx"
,
Pins
(
"AG13"
)),
# Arduino_IO0
IOStandard
(
"3.3-V LVTTL"
),
Misc
(
"WEAK_PULL_UP_RESISTOR ON"
),
Misc
(
"CURRENT_STRENGTH_NEW
\
"
MAXIMUM CURRENT
\
"
"
)
),
(
"g_sensor"
,
0
,
...
...
@@ -55,13 +57,13 @@ _io = [
),
(
"hdmi"
,
0
,
Subsignal
(
"tx_d_r"
,
Pins
(
"AS12 AE12 W8 Y8 AD11 AD10 AE11 Y5"
)),
Subsignal
(
"tx_d_g"
,
Pins
(
"AF10 Y4 AE9 AB4 AE7 AF6 AF8 AF5"
)),
Subsignal
(
"tx_d_b"
,
Pins
(
"AE4 AH2 AH4 AH5 AH6 AG6 AF9 AE8"
)),
Subsignal
(
"tx_clk"
,
Pins
(
"AG5"
)),
Subsignal
(
"tx_de"
,
Pins
(
"AD19"
)),
Subsignal
(
"tx_hs"
,
Pins
(
"T8"
)),
Subsignal
(
"tx_vs"
,
Pins
(
"V13"
)),
Subsignal
(
"tx_d_r"
,
Pins
(
"AS12 AE12 W8 Y8 AD11 AD10 AE11 Y5"
)
,
Misc
(
"FAST_OUTPUT_REGISTER ON"
)
),
Subsignal
(
"tx_d_g"
,
Pins
(
"AF10 Y4 AE9 AB4 AE7 AF6 AF8 AF5"
)
,
Misc
(
"FAST_OUTPUT_REGISTER ON"
)
),
Subsignal
(
"tx_d_b"
,
Pins
(
"AE4 AH2 AH4 AH5 AH6 AG6 AF9 AE8"
)
,
Misc
(
"FAST_OUTPUT_REGISTER ON"
)
),
Subsignal
(
"tx_clk"
,
Pins
(
"AG5"
)
,
Misc
(
"FAST_OUTPUT_REGISTER ON"
)
),
Subsignal
(
"tx_de"
,
Pins
(
"AD19"
)
,
Misc
(
"FAST_OUTPUT_REGISTER ON"
)
),
Subsignal
(
"tx_hs"
,
Pins
(
"T8"
)
,
Misc
(
"FAST_OUTPUT_REGISTER ON"
)
),
Subsignal
(
"tx_vs"
,
Pins
(
"V13"
)
,
Misc
(
"FAST_OUTPUT_REGISTER ON"
)
),
Subsignal
(
"tx_int"
,
Pins
(
"AF11"
)),
IOStandard
(
"3.3-V LVTTL"
)
),
...
...
@@ -90,13 +92,14 @@ _mister_sdram_module_io = [
"AC22 C12 AB26 AD17 D12"
)),
Subsignal
(
"dq"
,
Pins
(
"E8 V12 D11 W12 AH13 D8 AH14 AF7"
,
"AE24 AD23 AE6 AE23 AG14 AD5 AF4 AH3"
)),
"AE24 AD23 AE6 AE23 AG14 AD5 AF4 AH3"
),
Misc
(
"FAST_OUTPUT_ENABLE_REGISTER ON"
),
Misc
(
"FAST_INPUT_REGISTER ON"
)),
Subsignal
(
"ba"
,
Pins
(
"Y17 AB25"
)),
Subsignal
(
"cas_n"
,
Pins
(
"AA18"
)),
Subsignal
(
"cs_n"
,
Pins
(
"Y18"
)),
Subsignal
(
"ras_n"
,
Pins
(
"W14"
)),
Subsignal
(
"we_n"
,
Pins
(
"AA19"
)),
IOStandard
(
"3.3-V LVTTL"
)
IOStandard
(
"3.3-V LVTTL"
)
,
Misc
(
"CURRENT_STRENGTH_NEW
\
"
MAXIMUM CURRENT
\
"
"
),
Misc
(
"FAST_OUTPUT_REGISTER ON"
),
Misc
(
"ALLOW_SYNCH_CTRL_USAGE OFF"
)
),
(
"spisdcard"
,
0
,
...
...
@@ -104,14 +107,23 @@ _mister_sdram_module_io = [
Subsignal
(
"mosi"
,
Pins
(
"AF27"
)),
Subsignal
(
"cs_n"
,
Pins
(
"AF28"
)),
Subsignal
(
"miso"
,
Pins
(
"AF25"
)),
IOStandard
(
"3.3-V LVTTL"
)
IOStandard
(
"3.3-V LVTTL"
),
Misc
(
"CURRENT_STRENGTH_NEW
\
"
MAXIMUM CURRENT
\
"
"
),
Misc
(
"WEAK_PULL_UP_RESISTOR ON"
)
),
(
"sdcard"
,
0
,
Subsignal
(
"data"
,
Pins
(
"AF25 AF23 AD26 AF28"
),
Misc
(
"WEAK_PULL_UP_RESISTOR ON"
)),
Subsignal
(
"cmd"
,
Pins
(
"AF27"
),
Misc
(
"WEAK_PULL_UP_RESISTOR ON"
)),
Subsignal
(
"clk"
,
Pins
(
"AH26"
)),
Subsignal
(
"cd"
,
Pins
(
"AH7"
),
Misc
(
"WEAK_PULL_UP_RESISTOR ON"
)),
IOStandard
(
"3.3-V LVTTL"
),
Misc
(
"CURRENT_STRENGTH_NEW
\
"
MAXIMUM CURRENT
\
"
"
),
),
(
"mister_outputs"
,
0
,
Subsignal
(
"led_user"
,
Pins
(
"Y15"
)),
Subsignal
(
"led_hdd"
,
Pins
(
"AA15"
)),
Subsignal
(
"led_power"
,
Pins
(
"AG28"
)),
IOStandard
(
"3.3-V LVTTL"
)
IOStandard
(
"3.3-V LVTTL"
)
,
Misc
(
"WEAK_PULL_UP_RESISTOR ON"
),
Misc
(
"CURRENT_STRENGTH_NEW
\
"
MAXIMUM CURRENT
\
"
"
)
),
(
"vga"
,
0
,
...
...
@@ -120,8 +132,8 @@ _mister_sdram_module_io = [
Subsignal
(
"blue"
,
Pins
(
"AG21 AA20 AE22 AF22 AH23 AH21"
)),
Subsignal
(
"hsync"
,
Pins
(
"AH22"
)),
Subsignal
(
"vsync"
,
Pins
(
"AG24"
)),
Subsignal
(
"en"
,
Pins
(
"AH27"
)),
IOStandard
(
"3.3-V LVTTL"
)
Subsignal
(
"en"
,
Pins
(
"AH27"
)
,
Misc
(
"WEAK_PULL_UP_RESISTOR ON"
)
),
IOStandard
(
"3.3-V LVTTL"
)
,
Misc
(
"CURRENT_STRENGTH_NEW 8MA"
)
),
]
...
...
litex_boards/targets/de10nano.py
View file @
89c5bf43
...
...
@@ -21,16 +21,20 @@ from litex.soc.integration.builder import *
from
litex.soc.cores.led
import
LedChaser
from
litedram.modules
import
AS4C32M16
from
litedram.phy
import
GENSDRPHY
from
litedram.phy
import
GENSDRPHY
,
HalfRateGENSDRPHY
from
litevideo.terminal.core
import
Terminal
# CRG ----------------------------------------------------------------------------------------------
class
_CRG
(
Module
):
def
__init__
(
self
,
platform
,
sys_clk_freq
,
with_sdram
=
False
):
def
__init__
(
self
,
platform
,
sys_clk_freq
,
with_sdram
=
False
,
sdram_sys2x
=
False
):
self
.
clock_domains
.
cd_sys
=
ClockDomain
()
self
.
clock_domains
.
cd_sys_ps
=
ClockDomain
(
reset_less
=
True
)
if
sdram_sys2x
:
self
.
clock_domains
.
cd_sys2x
=
ClockDomain
()
self
.
clock_domains
.
cd_sys2x_ps
=
ClockDomain
(
reset_less
=
True
)
else
:
self
.
clock_domains
.
cd_sys_ps
=
ClockDomain
(
reset_less
=
True
)
self
.
clock_domains
.
cd_vga
=
ClockDomain
(
reset_less
=
True
)
# # #
...
...
@@ -41,17 +45,22 @@ class _CRG(Module):
self
.
submodules
.
pll
=
pll
=
CycloneVPLL
(
speedgrade
=
"-I7"
)
pll
.
register_clkin
(
clk50
,
50e6
)
pll
.
create_clkout
(
self
.
cd_sys
,
sys_clk_freq
)
pll
.
create_clkout
(
self
.
cd_sys_ps
,
sys_clk_freq
,
phase
=
90
)
if
sdram_sys2x
:
pll
.
create_clkout
(
self
.
cd_sys2x
,
2
*
sys_clk_freq
)
pll
.
create_clkout
(
self
.
cd_sys2x_ps
,
2
*
sys_clk_freq
,
phase
=
90
)
else
:
pll
.
create_clkout
(
self
.
cd_sys_ps
,
sys_clk_freq
,
phase
=
90
)
pll
.
create_clkout
(
self
.
cd_vga
,
25e6
)
# SDRAM clock
if
with_sdram
:
self
.
specials
+=
DDROutput
(
1
,
0
,
platform
.
request
(
"sdram_clock"
),
ClockSignal
(
"sys_ps"
))
sdram_clk
=
ClockSignal
(
"sys2x_ps"
if
sdram_sys2x
else
"sys_ps"
)
self
.
specials
+=
DDROutput
(
1
,
0
,
platform
.
request
(
"sdram_clock"
),
sdram_clk
)
# BaseSoC ------------------------------------------------------------------------------------------
class
BaseSoC
(
SoCCore
):
def
__init__
(
self
,
sys_clk_freq
=
int
(
50e6
),
with_mister_sdram
=
False
,
with_mister_vga
=
False
,
**
kwargs
):
def
__init__
(
self
,
sys_clk_freq
=
int
(
50e6
),
with_mister_sdram
=
True
,
with_mister_vga
=
False
,
sdram_sys2x
=
False
,
**
kwargs
):
platform
=
de10nano
.
Platform
()
# SoCCore ----------------------------------------------------------------------------------
...
...
@@ -61,14 +70,19 @@ class BaseSoC(SoCCore):
**
kwargs
)
# CRG --------------------------------------------------------------------------------------
self
.
submodules
.
crg
=
_CRG
(
platform
,
sys_clk_freq
,
with_sdram
=
with_mister_sdram
)
self
.
submodules
.
crg
=
_CRG
(
platform
,
sys_clk_freq
,
with_sdram
=
with_mister_sdram
,
sdram_sys2x
=
sdram_sys2x
)
# SDR SDRAM --------------------------------------------------------------------------------
if
with_mister_sdram
and
not
self
.
integrated_main_ram_size
:
self
.
submodules
.
sdrphy
=
GENSDRPHY
(
platform
.
request
(
"sdram"
))
if
sdram_sys2x
:
self
.
submodules
.
sdrphy
=
HalfRateGENSDRPHY
(
platform
.
request
(
"sdram"
))
rate
=
"1:2"
else
:
self
.
submodules
.
sdrphy
=
GENSDRPHY
(
platform
.
request
(
"sdram"
))
rate
=
"1:1"
self
.
add_sdram
(
"sdram"
,
phy
=
self
.
sdrphy
,
module
=
AS4C32M16
(
s
elf
.
clk_freq
,
"1:1"
),
module
=
AS4C32M16
(
s
ys_clk_freq
,
rate
),
origin
=
self
.
mem_map
[
"main_ram"
],
size
=
kwargs
.
get
(
"max_sdram_size"
,
0x40000000
),
l2_cache_size
=
kwargs
.
get
(
"l2_size"
,
8192
),
...
...
@@ -105,10 +119,12 @@ def main():
soc_sdram_args
(
parser
)
parser
.
add_argument
(
"--with-mister-sdram"
,
action
=
"store_true"
,
help
=
"Enable SDRAM with MiSTer expansion board"
)
parser
.
add_argument
(
"--with-mister-vga"
,
action
=
"store_true"
,
help
=
"Enable VGA with Mister expansion board"
)
parser
.
add_argument
(
"--sdram-sys2x"
,
action
=
"store_true"
,
help
=
"Use double frequency for SDRAM PHY"
)
args
=
parser
.
parse_args
()
soc
=
BaseSoC
(
with_mister_sdram
=
args
.
with_mister_sdram
,
with_mister_vga
=
args
.
with_mister_vga
,
sdram_sys2x
=
args
.
sdram_sys2x
,
**
soc_sdram_argdict
(
args
))
builder
=
Builder
(
soc
,
**
builder_argdict
(
args
))
builder
.
build
(
run
=
args
.
build
)
...
...
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