Commit 7a9f1754 authored by Florent Kermarrec's avatar Florent Kermarrec

targets/pcie: remove force of csr_data_width to 32 (this is now the default)...

targets/pcie: remove force of csr_data_width to 32 (this is now the default) but just add a check on the pcie block.
parent 4401fec1
...@@ -108,6 +108,7 @@ class BaseSoC(SoCCore): ...@@ -108,6 +108,7 @@ class BaseSoC(SoCCore):
# PCIe ------------------------------------------------------------------------------------- # PCIe -------------------------------------------------------------------------------------
if with_pcie: if with_pcie:
assert self.csr_data_width == 32
# PHY # PHY
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128, data_width = 128,
...@@ -172,10 +173,7 @@ def main(): ...@@ -172,10 +173,7 @@ def main():
soc_sdram_args(parser) soc_sdram_args(parser)
args = parser.parse_args() args = parser.parse_args()
# Enforce arguments soc = BaseSoC(with_pcie=args.with_pcie, **soc_sdram_argdict(args))
args.csr_data_width = 32
soc = BaseSoC(with_pcie=args.with_pcie, **soc_sdram_argdict(args))
if args.with_spi_sdcard: if args.with_spi_sdcard:
soc.add_spi_sdcard() soc.add_spi_sdcard()
......
...@@ -91,6 +91,7 @@ class BaseSoC(SoCCore): ...@@ -91,6 +91,7 @@ class BaseSoC(SoCCore):
# PCIe ------------------------------------------------------------------------------------- # PCIe -------------------------------------------------------------------------------------
if with_pcie: if with_pcie:
assert self.csr_data_width == 32
# PHY # PHY
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128, data_width = 128,
...@@ -144,9 +145,6 @@ def main(): ...@@ -144,9 +145,6 @@ def main():
soc_sdram_args(parser) soc_sdram_args(parser)
args = parser.parse_args() args = parser.parse_args()
# Enforce arguments
args.csr_data_width = 32
platform = aller.Platform() platform = aller.Platform()
soc = BaseSoC(platform, with_pcie=args.with_pcie, **soc_sdram_argdict(args)) soc = BaseSoC(platform, with_pcie=args.with_pcie, **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
......
...@@ -97,6 +97,7 @@ class BaseSoC(SoCCore): ...@@ -97,6 +97,7 @@ class BaseSoC(SoCCore):
# PCIe ------------------------------------------------------------------------------------- # PCIe -------------------------------------------------------------------------------------
if with_pcie: if with_pcie:
assert self.csr_data_width == 32
# PHY # PHY
self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"), self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128, data_width = 128,
...@@ -150,9 +151,6 @@ def main(): ...@@ -150,9 +151,6 @@ def main():
soc_sdram_args(parser) soc_sdram_args(parser)
args = parser.parse_args() args = parser.parse_args()
# Enforce arguments
args.csr_data_width = 32
soc = BaseSoC(with_pcie=args.with_pcie, **soc_sdram_argdict(args)) soc = BaseSoC(with_pcie=args.with_pcie, **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build) builder.build(run=args.build)
......
...@@ -56,6 +56,7 @@ class BaseSoC(SoCCore): ...@@ -56,6 +56,7 @@ class BaseSoC(SoCCore):
# PCIe ------------------------------------------------------------------------------------- # PCIe -------------------------------------------------------------------------------------
if with_pcie: if with_pcie:
assert self.csr_data_width == 32
# PHY # PHY
self.submodules.pcie_phy = USPHBMPCIEPHY(platform, platform.request("pcie_x4"), self.submodules.pcie_phy = USPHBMPCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128, data_width = 128,
...@@ -109,9 +110,6 @@ def main(): ...@@ -109,9 +110,6 @@ def main():
soc_core_args(parser) soc_core_args(parser)
args = parser.parse_args() args = parser.parse_args()
# Enforce arguments
args.csr_data_width = 32
soc = BaseSoC(with_pcie=args.with_pcie, **soc_core_argdict(args)) soc = BaseSoC(with_pcie=args.with_pcie, **soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build) builder.build(run=args.build)
......
...@@ -88,6 +88,7 @@ class BaseSoC(SoCCore): ...@@ -88,6 +88,7 @@ class BaseSoC(SoCCore):
# PCIe ------------------------------------------------------------------------------------- # PCIe -------------------------------------------------------------------------------------
if with_pcie: if with_pcie:
assert self.csr_data_width == 32
# PHY # PHY
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128, data_width = 128,
...@@ -135,9 +136,6 @@ def main(): ...@@ -135,9 +136,6 @@ def main():
soc_sdram_args(parser) soc_sdram_args(parser)
args = parser.parse_args() args = parser.parse_args()
# Enforce arguments
args.csr_data_width = 32
platform = nereid.Platform() platform = nereid.Platform()
soc = BaseSoC(platform, with_pcie=args.with_pcie, **soc_sdram_argdict(args)) soc = BaseSoC(platform, with_pcie=args.with_pcie, **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
......
...@@ -91,6 +91,7 @@ class BaseSoC(SoCCore): ...@@ -91,6 +91,7 @@ class BaseSoC(SoCCore):
# PCIe ------------------------------------------------------------------------------------- # PCIe -------------------------------------------------------------------------------------
if with_pcie: if with_pcie:
assert self.csr_data_width == 32
# PHY # PHY
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"),
data_width = 64, data_width = 64,
...@@ -144,9 +145,6 @@ def main(): ...@@ -144,9 +145,6 @@ def main():
soc_sdram_args(parser) soc_sdram_args(parser)
args = parser.parse_args() args = parser.parse_args()
# Enforce arguments
args.csr_data_width = 32
platform = tagus.Platform() platform = tagus.Platform()
soc = BaseSoC(platform, with_pcie=args.with_pcie, **soc_sdram_argdict(args)) soc = BaseSoC(platform, with_pcie=args.with_pcie, **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
......
...@@ -95,6 +95,7 @@ class BaseSoC(SoCCore): ...@@ -95,6 +95,7 @@ class BaseSoC(SoCCore):
# PCIe ------------------------------------------------------------------------------------- # PCIe -------------------------------------------------------------------------------------
if with_pcie: if with_pcie:
assert self.csr_data_width == 32
# PHY # PHY
self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"), self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128, data_width = 128,
...@@ -149,10 +150,7 @@ def main(): ...@@ -149,10 +150,7 @@ def main():
soc_sdram_args(parser) soc_sdram_args(parser)
args = parser.parse_args() args = parser.parse_args()
# Enforce arguments soc = BaseSoC(
args.csr_data_width = 32
soc = BaseSoC(
ddram_channel = int(args.ddram_channel, 0), ddram_channel = int(args.ddram_channel, 0),
with_pcie = args.with_pcie, with_pcie = args.with_pcie,
**soc_sdram_argdict(args)) **soc_sdram_argdict(args))
......
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