diff --git a/litex_boards/targets/acorn_cle_215.py b/litex_boards/targets/acorn_cle_215.py index bbde93e73af9a831266b3f2698abe1a423c51f62..c262aaac1e953ff681df6b713d83be815f775fbf 100755 --- a/litex_boards/targets/acorn_cle_215.py +++ b/litex_boards/targets/acorn_cle_215.py @@ -108,6 +108,7 @@ class BaseSoC(SoCCore): # PCIe ------------------------------------------------------------------------------------- if with_pcie: + assert self.csr_data_width == 32 # PHY self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width = 128, @@ -172,10 +173,7 @@ def main(): soc_sdram_args(parser) args = parser.parse_args() - # Enforce arguments - args.csr_data_width = 32 - - soc = BaseSoC(with_pcie=args.with_pcie, **soc_sdram_argdict(args)) + soc = BaseSoC(with_pcie=args.with_pcie, **soc_sdram_argdict(args)) if args.with_spi_sdcard: soc.add_spi_sdcard() diff --git a/litex_boards/targets/aller.py b/litex_boards/targets/aller.py index cc18085553074a2adec761c6cb71a0cf1983a967..aec5a6d23f44bc6b657f952855094fc7c7a9da4c 100755 --- a/litex_boards/targets/aller.py +++ b/litex_boards/targets/aller.py @@ -91,6 +91,7 @@ class BaseSoC(SoCCore): # PCIe ------------------------------------------------------------------------------------- if with_pcie: + assert self.csr_data_width == 32 # PHY self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width = 128, @@ -144,9 +145,6 @@ def main(): soc_sdram_args(parser) args = parser.parse_args() - # Enforce arguments - args.csr_data_width = 32 - platform = aller.Platform() soc = BaseSoC(platform, with_pcie=args.with_pcie, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) diff --git a/litex_boards/targets/alveo_u250.py b/litex_boards/targets/alveo_u250.py index 677946dd38bd5bda11ac477d3f51a29ef1665062..65c7623dbee876b71d422d99797b25270fff53dd 100755 --- a/litex_boards/targets/alveo_u250.py +++ b/litex_boards/targets/alveo_u250.py @@ -97,6 +97,7 @@ class BaseSoC(SoCCore): # PCIe ------------------------------------------------------------------------------------- if with_pcie: + assert self.csr_data_width == 32 # PHY self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"), data_width = 128, @@ -150,9 +151,6 @@ def main(): soc_sdram_args(parser) args = parser.parse_args() - # Enforce arguments - args.csr_data_width = 32 - soc = BaseSoC(with_pcie=args.with_pcie, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/fk33.py b/litex_boards/targets/fk33.py index d042e425e7a349fad51e2e3e179b6e0c93c7e82a..c002c8deb72ea294745883afa3c2c79eabec0134 100755 --- a/litex_boards/targets/fk33.py +++ b/litex_boards/targets/fk33.py @@ -56,6 +56,7 @@ class BaseSoC(SoCCore): # PCIe ------------------------------------------------------------------------------------- if with_pcie: + assert self.csr_data_width == 32 # PHY self.submodules.pcie_phy = USPHBMPCIEPHY(platform, platform.request("pcie_x4"), data_width = 128, @@ -109,9 +110,6 @@ def main(): soc_core_args(parser) args = parser.parse_args() - # Enforce arguments - args.csr_data_width = 32 - soc = BaseSoC(with_pcie=args.with_pcie, **soc_core_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/nereid.py b/litex_boards/targets/nereid.py index 30dc47a2ee46c872c5e9b988d5a7783104ec7a1e..a2f562f19b80a18c3d81b2bc7bf965c1d614dd61 100755 --- a/litex_boards/targets/nereid.py +++ b/litex_boards/targets/nereid.py @@ -88,6 +88,7 @@ class BaseSoC(SoCCore): # PCIe ------------------------------------------------------------------------------------- if with_pcie: + assert self.csr_data_width == 32 # PHY self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width = 128, @@ -135,9 +136,6 @@ def main(): soc_sdram_args(parser) args = parser.parse_args() - # Enforce arguments - args.csr_data_width = 32 - platform = nereid.Platform() soc = BaseSoC(platform, with_pcie=args.with_pcie, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) diff --git a/litex_boards/targets/tagus.py b/litex_boards/targets/tagus.py index e716a85c17c0836958193572a58ad8f690e8dda4..97e4d283396e39efde5d3589de84d1a98094f904 100755 --- a/litex_boards/targets/tagus.py +++ b/litex_boards/targets/tagus.py @@ -91,6 +91,7 @@ class BaseSoC(SoCCore): # PCIe ------------------------------------------------------------------------------------- if with_pcie: + assert self.csr_data_width == 32 # PHY self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), data_width = 64, @@ -144,9 +145,6 @@ def main(): soc_sdram_args(parser) args = parser.parse_args() - # Enforce arguments - args.csr_data_width = 32 - platform = tagus.Platform() soc = BaseSoC(platform, with_pcie=args.with_pcie, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) diff --git a/litex_boards/targets/xcu1525.py b/litex_boards/targets/xcu1525.py index 3263b692afdd810d7024d54b3c734944cbf3bfac..f246b30416ccc3a49d7701bb234cbd0cea6508be 100755 --- a/litex_boards/targets/xcu1525.py +++ b/litex_boards/targets/xcu1525.py @@ -95,6 +95,7 @@ class BaseSoC(SoCCore): # PCIe ------------------------------------------------------------------------------------- if with_pcie: + assert self.csr_data_width == 32 # PHY self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"), data_width = 128, @@ -149,10 +150,7 @@ def main(): soc_sdram_args(parser) args = parser.parse_args() - # Enforce arguments - args.csr_data_width = 32 - - soc = BaseSoC( + soc = BaseSoC( ddram_channel = int(args.ddram_channel, 0), with_pcie = args.with_pcie, **soc_sdram_argdict(args))