diff --git a/litex_boards/platforms/versa_ecp5.py b/litex_boards/platforms/versa_ecp5.py index f6011b753f9ca91f377ce1f1a967fa78981efd58..67d389d0e07c2689986106bbce0961294e55b925 100644 --- a/litex_boards/platforms/versa_ecp5.py +++ b/litex_boards/platforms/versa_ecp5.py @@ -53,9 +53,11 @@ _io = [ ("alpha_led", 11, Pins("P16"), IOStandard("LVCMOS25")), ("alpha_led", 12, Pins("R16"), IOStandard("LVCMOS25")), ("alpha_led", 13, Pins("R17"), IOStandard("LVCMOS25")), - ("alpha_led", 14, Pins("U1"), IOStandard("LVCMOS25")), + ("alpha_led", 14, Pins("U1"), IOStandard("LVCMOS33")), ("alpha_led", 15, Pins("T16"), IOStandard("LVCMOS25")), # Not wired on Versa board, but makes GPIO bank 16 bits. Future expansion? - ("alpha_leds", 0, Pins("M20 L18 M19 L16 L17 M18 N16 M17 N18 P17 N17 P16 R16 R17 U1 T16"), IOStandard("LVCMOS25")), # T16 not wired on Versa board, but makes GPIO bank 16 bits. Future expansion? + # T16 not wired on Versa board, but makes GPIO bank 16 bits. Future expansion? + ("alpha_leds", 0, Pins("M20 L18 M19 L16 L17 M18 N16 M17 N18 P17 N17 P16 R16 R17 U1 T16"), + IOStandard("LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS33 LVCMOS25")), # Serial ("serial", 0, @@ -205,6 +207,16 @@ _io = [ Subsignal("data_direction", Pins("D15"), IOStandard("LVCMOS33")), ), + # Versa Flash device + # Also contains FPGA bistream, USRMCLK block required for clock output + ("bmcspiflash4x", 0, + Subsignal("cs_n", Pins("R2")), + Subsignal("dq", Pins("W2 V2 Y2 W1")), + IOStandard("LVCMOS33"), + Misc("SLEWRATE=SLOW"), + Misc("DRIVE=16"), + ), + ("hostspiflash4x", 0, Subsignal("cs_n", Pins("A14")), Subsignal("clk", Pins("A12")), diff --git a/litex_boards/targets/versa_ecp5.py b/litex_boards/targets/versa_ecp5.py index 79f42b4a496e14e7e38fc93f216f959a5d5c9b67..b292f17839d92b6a2a5553787fba64086e4a4936 100755 --- a/litex_boards/targets/versa_ecp5.py +++ b/litex_boards/targets/versa_ecp5.py @@ -98,15 +98,17 @@ class BaseSoC(SoCCore): "hostxicsicp" : 0xc3000000, "hostxicsics" : 0xc3001000, "ethmac" : 0xc3002000, - "hostspiflashcfg" : 0xc3007000, + "bmcspiflashcfg" : 0xc3004000, + "hostspiflashcfg" : 0xc3005000, "simplertc" : 0xc3008000, "openfsimaster" : 0xc3009000, "i2cmaster1" : 0xc300a000, "i2cmaster2" : 0xc300a020, "i2cmaster3" : 0xc300a040, "i2cmaster4" : 0xc300a060, - "hostspiflash" : 0xc4000000, - "hostlpcslave" : 0xcb000000, + "bmcspiflash" : 0xc4000000, + "hostspiflash" : 0xc8000000, + "hostlpcslave" : 0xcc000000, } mem_map.update(SoCCore.mem_map) @@ -121,7 +123,7 @@ class BaseSoC(SoCCore): } interrupt_map.update(SoCCore.interrupt_map) - def __init__(self, sys_clk_freq=int(50e6), device="LFE5UM5G", with_ethernet=False, with_etherbone=False, with_openfsi_master=True, with_hostspiflash=True, with_hostlpcslave=True, with_i2c_masters=True, with_simple_rtc=True, eth_ip="192.168.1.50", eth_phy=0, toolchain="trellis", **kwargs): + def __init__(self, sys_clk_freq=int(50e6), device="LFE5UM5G", with_ethernet=False, with_etherbone=False, with_openfsi_master=True, with_bmcspiflash=True, with_hostspiflash=True, with_hostlpcslave=True, with_i2c_masters=True, with_simple_rtc=True, eth_ip="192.168.1.50", eth_phy=0, toolchain="trellis", **kwargs): platform = versa_ecp5.Platform(toolchain=toolchain, device=device) # Reduce resource wastage on ECP5 @@ -193,29 +195,53 @@ class BaseSoC(SoCCore): self.add_etherbone(phy=self.ethphy, ip_address=eth_ip) # Debug pad locator - debug2_pads = platform.request("debug_port_2") + try: + debug2_pads = platform.request("debug_port_2") + except: + debug2_pads = None try: lpc_debug_mirror_clock_pad = platform.request("lpc_debug_mirror_clock") except: lpc_debug_mirror_clock_pad = Signal() + # BMC SPI Flash (Tercel core) ------------------------------------------------------------- + if with_bmcspiflash: + bmcspiflash4x_pads = platform.request("bmcspiflash4x") + self.bmc_spi_dq_debug = [Signal(), Signal(), Signal(), Signal(), Signal(), Signal()] + self.submodules.bmcspiflash = TercelSPI( + platform = platform, + pads = bmcspiflash4x_pads, + lattice_ecp5_usrmclk = True, + debug_signals = self.bmc_spi_dq_debug, + clk_freq = sys_clk_freq, + endianness = self.cpu.endianness, + adr_offset = self.mem_map.get("bmcspiflash", None)) + self.add_csr("bmcspiflash") + bmcspiflash_size = 16*mB + bmcspiflash_region = SoCRegion(origin=self.mem_map.get("bmcspiflash", None), size=bmcspiflash_size, cached=False) + self.bus.add_slave(name="bmcspiflash", slave=self.bmcspiflash.bus, region=bmcspiflash_region) + bmcspiflashcfg_size = 128 + bmcspiflashcfg_region = SoCRegion(origin=self.mem_map.get("bmcspiflashcfg", None), size=bmcspiflashcfg_size, cached=False) + self.bus.add_slave(name="bmcspiflashcfg", slave=self.bmcspiflash.cfg_bus, region=bmcspiflashcfg_region) + # Host SPI Flash (Tercel core) ------------------------------------------------------------- if with_hostspiflash: hostspiflash4x_pads = platform.request("hostspiflash4x") self.host_spi_dq_debug = [Signal(), Signal(), Signal(), Signal(), Signal(), Signal()] self.submodules.hostspiflash = TercelSPI( - platform = platform, - pads = hostspiflash4x_pads, - debug_signals = self.host_spi_dq_debug, - clk_freq = sys_clk_freq, - endianness = self.cpu.endianness, - adr_offset = self.mem_map.get("hostspiflash", None)) + platform = platform, + pads = hostspiflash4x_pads, + lattice_ecp5_usrmclk = False, + debug_signals = self.host_spi_dq_debug, + clk_freq = sys_clk_freq, + endianness = self.cpu.endianness, + adr_offset = self.mem_map.get("hostspiflash", None)) self.add_csr("hostspiflash") - hostspiflash_size = 64*mB - hostspiflash_region = SoCRegion(origin=self.mem_map.get("hostspiflash", None), size=hostspiflash_size, cached=False) + hostspiflash_size = 64*mB + hostspiflash_region = SoCRegion(origin=self.mem_map.get("hostspiflash", None), size=hostspiflash_size, cached=False) self.bus.add_slave(name="hostspiflash", slave=self.hostspiflash.bus, region=hostspiflash_region) - hostspiflashcfg_size = 128 - hostspiflashcfg_region = SoCRegion(origin=self.mem_map.get("hostspiflashcfg", None), size=hostspiflashcfg_size, cached=False) + hostspiflashcfg_size = 128 + hostspiflashcfg_region = SoCRegion(origin=self.mem_map.get("hostspiflashcfg", None), size=hostspiflashcfg_size, cached=False) self.bus.add_slave(name="hostspiflashcfg", slave=self.hostspiflash.cfg_bus, region=hostspiflashcfg_region) # Host LPC Slave (Aquila core) ------------------------------------------------------------- @@ -258,7 +284,7 @@ class BaseSoC(SoCCore): #self.comb += debug2_pads.led_9.eq(self.host_spi_dq_debug[1]) #self.comb += debug2_pads.led_8.eq(self.host_spi_dq_debug[0]) - if with_hostlpcslave: + if with_hostlpcslave and debug2_pads is not None: self.comb += debug2_pads.led_15.eq(self.host_lpc_debug[7]) self.comb += debug2_pads.led_14.eq(self.host_lpc_debug[6]) self.comb += debug2_pads.led_13.eq(self.host_lpc_debug[5]) @@ -376,6 +402,7 @@ def main(): device = args.device, with_ethernet = args.with_ethernet, with_etherbone = args.with_etherbone, + with_bmcspiflash = True, with_hostspiflash = True, with_hostlpcslave = True, with_openfsi_master = True,