From 71724d67ca03843a779996b2f9e7ea2fd659f5d3 Mon Sep 17 00:00:00 2001 From: Raptor Engineering Development Team Date: Tue, 30 Mar 2021 13:17:23 -0500 Subject: [PATCH] Annotate Kestrel board control file on the ECP5 This also explicitly sets the CSR stride to avoid breakage under future LiteX upstream changes. This change does not alter the generated HDL or bitstream. --- litex_boards/targets/versa_ecp5.py | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/litex_boards/targets/versa_ecp5.py b/litex_boards/targets/versa_ecp5.py index dfe8049..77e847c 100755 --- a/litex_boards/targets/versa_ecp5.py +++ b/litex_boards/targets/versa_ecp5.py @@ -124,8 +124,18 @@ class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(50e6), device="LFE5UM5G", with_ethernet=False, with_etherbone=False, with_openfsi_master=True, with_hostspiflash=True, with_hostlpcslave=True, with_i2c_masters=True, with_simple_rtc=True, eth_ip="192.168.1.50", eth_phy=0, toolchain="trellis", **kwargs): platform = versa_ecp5.Platform(toolchain=toolchain, device=device) + # Reduce resource wastage on ECP5 kwargs["csr_address_width"] = 14 kwargs["csr_data_width"] = 8 + kwargs["csr_paging"] = 0x800 + + # Disable timer uptime counter + # Microwatt already provides an architecturally-defined timer with interrupt (decrementer), + # so the LiteX one just wastes resources in Kestrel. + # FIXME: The entire timer could be removed if the LiteX BIOS could make use of the POWER decrementer, + # freeing resources for something else. + kwargs["with_timer"] = True + kwargs["timer_uptime"] = False # FIXME: adapt integrated rom size for Microwatt if kwargs.get("cpu_type", None) == "microwatt": -- 2.30.2