Commit 6f558a5d authored by Hans Baier's avatar Hans Baier

Add board support for Terasic/Arrow DECA board

parent bc255a6a
...@@ -128,6 +128,7 @@ The Colorlight5A is a very nice board to start with, cheap, powerful, easy to us ...@@ -128,6 +128,7 @@ The Colorlight5A is a very nice board to start with, cheap, powerful, easy to us
| C10LPRefKit | Intel Cyclone10 | 10CL055 | 50MHz | FTDI | 16-bit 32MB SDR | No | 100Mbps MII | 16MB QSPI | No | | C10LPRefKit | Intel Cyclone10 | 10CL055 | 50MHz | FTDI | 16-bit 32MB SDR | No | 100Mbps MII | 16MB QSPI | No |
| De0Nano | Intel Cyclone4 | EP4CE22F | 50MHz | FTDI | 16-bit 32MB SDR | No | No | No | No | | De0Nano | Intel Cyclone4 | EP4CE22F | 50MHz | FTDI | 16-bit 32MB SDR | No | No | No | No |
| De10Lite | Intel MAX10 | 10M50DA | 50MHz | IOs | 16-bit 64MB SDR | No | No | No | No | | De10Lite | Intel MAX10 | 10M50DA | 50MHz | IOs | 16-bit 64MB SDR | No | No | No | No |
| DECA | Intel MAX10 | 10M50DA | 50MHz | JTAG | 16-bit 512MG DDR3* | No | Yes | No | Yes |
| De10Nano | Intel Cyclone5 | 5CSEBA6 | 50MHz | IOs | 16-bit 32MB SDR | No | No | No | Yes | | De10Nano | Intel Cyclone5 | 5CSEBA6 | 50MHz | IOs | 16-bit 32MB SDR | No | No | No | Yes |
| Arrow SoCKit | Intel Cyclone5 | 5CSXFC6D6F31C8| 50MHz | JTAG | 32-bit 1GB DDR3* | No | No | No | No | | Arrow SoCKit | Intel Cyclone5 | 5CSXFC6D6F31C8| 50MHz | JTAG | 32-bit 1GB DDR3* | No | No | No | No |
| De1SoC | Intel Cyclone5 | 5CSEMA5 | 50MHz | IOs | 16-bit 64MB SDR | No | ? | ? | ? | | De1SoC | Intel Cyclone5 | 5CSEMA5 | 50MHz | IOs | 16-bit 64MB SDR | No | ? | ? | ? |
......
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#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2019 msloniewski <marcin.sloniewski@gmail.com>
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.build.io import DDROutput
from litex_boards.platforms import deca
from litex.soc.cores.clock import Max10PLL
from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
from litevideo.terminal.core import Terminal
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
# # #
# Clk / Rst
clk50 = platform.request("clk1_50")
# PLL
self.submodules.pll = pll = Max10PLL(speedgrade="-6")
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(clk50, 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(50e6), with_vga=False, **kwargs):
platform = deca.Platform()
# Defaults to UART over JTAG because no hardware uart is on the board
if kwargs["uart_name"] == "serial":
kwargs["uart_name"] = "jtag_atlantic"
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on DECA",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on DECA")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
builder_args(parser)
soc_sdram_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
**soc_sdram_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".sof"))
if __name__ == "__main__":
main()
...@@ -94,6 +94,7 @@ class TestTargets(unittest.TestCase): ...@@ -94,6 +94,7 @@ class TestTargets(unittest.TestCase):
# Intel Max10 # Intel Max10
platforms.append("de10lite") platforms.append("de10lite")
platforms.append("deca")
# Lattice iCE40 # Lattice iCE40
platforms.append("fomu_evt") platforms.append("fomu_evt")
......
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