Add missing README.md file from 03-18-2021 branch

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LiteX boards files # Kestrel SoftBMC Project
## SoC integration files
Copyright (c) 2020 - 2021 Raptor Engineering, LLC
Copyright 2012-2020 / LiteX-Hub community ====================================================
[![](https://github.com/litex-hub/litex-boards/workflows/ci/badge.svg)](https://github.com/litex-hub/litex-boards/actions) ![License](https://img.shields.io/badge/License-BSD%202--Clause-orange.svg) # What is it?
[> Intro Kestrel is the world's first full featured "soft" BMC SoC, designed for and tested on the ECP-5 series of FPGAs from Lattice using the NextPNR open source development flow on ppc64le. It is currently able to IPL a POWER9 host, such as the Blackbird and Talos II systems from Raptor Computing Systems [^1], completely independent of the ASpeed hard ASIC BMC integrated on those systems.
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<img src="https://user-images.githubusercontent.com/1450143/88511626-73792100-cfe5-11ea-8d3e-dbeea6314e15.JPG">
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<figcaption>
<p align="center">
From the very tiny Fomu to large PCIe accelerator boards....
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This repository contains the platforms/targets currently supported by LiteX: As a fully open HDL and open firmware / open software design using open tooling on open ISA systems, Kestrel allows a very high level of assurance regarding security, owner control, and trustability of this key component on modern systems.
- The platform provides the definition of the board: IOs, constraints, clocks, components + methods to load and flash the bitstream to it. # How to build
- The target provides a LiteX base design for the board that allows you to create a SoC (with or without a CPU) and integrate easily all the base components of your board: Ethernet, DRAM, PCIe, SPIFlash, SDCard, Leds, GPIOs, etc...
The targets can be used as a base to build more complex or custom SoCs. They are are for example directly reused by the [Linux-on-LiteX-VexRiscv](https://github.com/litex-hub/linux-on-litex-vexriscv) project that is just using a specific configuration (Linux-capable CPU, additional peripherals). Basing your design on provided targets allows to to reduce code duplication between very various projects. Building the Kestrel BMC for the ECP-5 FPGA on the Versa board is quite straightforward. We recommend the latest versions of NextPNR and related tooling be used, as we push these tools to their limits in many respects with this design. Kestrel is primarily developed on Debian Buster on Talos II or Blackbird hosts (ppc64le). Raptor strongly recommends that its development environment be used, as we will not be able to assist with issues encountered on other platforms. In particular, Raptor will not provide assistance with issues specific to either x86_64 systems or proprietary FPGA toolchains.
First make sure to install LiteX correctly by following the [installation guide](https://github.com/enjoy-digital/litex/wiki/Installation) and have a look at the [LiteX's wiki](https://github.com/enjoy-digital/litex/wiki) for [tutorials](https://github.com/enjoy-digital/litex/wiki/Tutorials-Resources), [examples of projects](https://github.com/enjoy-digital/litex/wiki/Projects) and more information to use/build FPGA designs with it. Please see the [Quick Start Guide](https://gitlab.raptorengineering.com/kestrel-collaboration/kestrel-litex/litex/-/wikis/Quick-Start) for setup instructions applicable to the standard Raptor development environment on POWER9. After the subrepositories are set up, simply run:
Each target provides a default configuration with a CPU, ROM, SRAM, UART, DRAM (if available), Ethernet (if available), etc... that can be simply built and loaded to the FPGA with: cd kestrel/litex/litex-boards/litex_boards/targets
./versa_ecp5.py --device=LFE5UM --cpu-type=microwatt --cpu-variant=standard+ghdl --build --nextpnr-seed 1
$ ./target.py --build --load # Updating the bitstream with new firmware
You can then open a terminal on the main UART of the board and interact with the LiteX BIOS: The bitstream is automatically stuffed with valid ROM contents, however, if a developer wishes to update the rom, the following sequence can be used:
<p align="center"><img src="https://raw.githubusercontent.com/enjoy-digital/litex/master/doc/bios_screenshot.png"></p> cd kestrel/litex/litex-boards/litex_boards/targets/build/versa_ecp5/gateware
ecpbram -i versa_ecp5.config -o versa_ecp5_stuffed.config -f rom.init -t rom_data.init
ecppack versa_ecp5_stuffed.config --svf versa_ecp5.svf --bit versa_ecp5.bit --bootaddr 0
But this is just the starting point to create your own hardware! You can then: # How to connect
- Change the CPU: add `--cpu-type=lm32, microwatt, serv, rocket, etc... ` ## POWER9 hosts
- Change the Bus standard: add `--bus-standard=wishbone, axi-lite` ### Interfaces
- Enable components: add `--with-ethernet --with-etherbone --with-sdcard etc...` The Kestrel soft BMC will require, at minimum, the following signals to be connected to a POWER9 host to allow the host to IPL:
- [Load application code to the CPU](https://github.com/enjoy-digital/litex/wiki/Load-Application-Code-To-CPU) over UART/Ethernet/SDCard, etc... - LPC
- Create a bridge with your computer to easily [access the main bus of your SoC](https://github.com/enjoy-digital/litex/wiki/Use-Host-Bridge-to-control-debug-a-SoC). - FSI
- Add a Logic Analyzer to your SoC to easily [observe/debug your design](https://github.com/enjoy-digital/litex/wiki/Use-LiteScope-To-Debug-A-SoC). - I2C (Platform control)
- Simulate your SoC and interact with it at decent speed with [LiteX Sim](https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_sim.py)/Verilator. - I2C (AVSBus)
- Integrate external cores/CPU to create your own design.
- etc... Of the four interfaces above, only FSI will require soldering to attach to the on-board 3.3V translator. On Blackbird, the three 3.3V FSI control lines (FSI_SOFT_CLK, FSI_SOFT_DAT, DBG_FSI0_DAT_EN) are available at R3200, R3202, and R7018 respectively (see photographs). Alternatively, if soldering is not desired, the FSI debug connector (J3200) can be utilized with an external voltage level translator circuit between the connector and the FPGA. Similarly, the Talos II mainboard should be able to be utilized as the host, but Raptor has not yet tested Kestrel on Talos II.
Please use `./target.py --help` to see the pre-built various possibilities. ![RCS Blackbird top-side FSI tap points](images/rcs/blackbird/fsi_tap_top.png) ![RCS Blackbird bottom-side FSI tap points](images/rcs/blackbird/fsi_tap_bottom.png)
Hoping you will find this useful and enjoy it, please contribute back if you make improvements that could be useful to others or find issues! When connecting the LPC bus to J10105, be sure to keep all lines as short as possible and length matched. Weak pull-ups (15kΩ) are required between the LPC data / frame / reset lines and +3.3V AUX (or 3.3V FPGA) power. No pull-up should be used on the clock line.
**A question or want to get in touch? Our IRC channel is [#litex at freenode.net](https://webchat.freenode.net/?channels=litex)** The I2C platform control lines are available at J10103, while the I2C AVSBus lines are available at J6902. Both headers are standard IDC stake pins.
> **Note:** All boards with >= 32MB of memory and enough logic can be considered as Linux Capable. In all cases, we recommend consulting the Blackbird (or Talos II) schematics along with the Versa ECP5 schematics while making the initial connections between the two boards. Special attention to high speed signal routing and grounding will help ensure a successful result.
### ASpeed BMC deactivation
[> Open-hardware boards In addition, the ASpeed BMC will need to be deactivated. This is slightly more difficult than might be expected, because the ASpeed BMC is pinstrapped in a way that it will actively interfere with the LPC lines if held in reset. As a result, the preferred way to isolate it from the mainboard is to allow it to boot, then issue the following commmands at the ASpeed BMC root console:
-----------------------
# Disable AST LPC pins
Fully open-hardware boards, the ECP5 and iCE40 ones are even usable with the open-source FPGA toolchains! devmem 0x1e6e20ac 32 0x00000000
| Name | FPGA Family | FPGA device | Sys-Clk | TTY | RAM | PCIe | Ethernet | Flash | SDCard | # Switch FSI GPIOs (H1,H2,H3) to input mode (Raptor Blackbird mainboards)
|--------------|---------------------|---------------|----------|------|---------------------|-----------|----------------|-------------|--------| echo gpio-fsi > /sys/bus/platform/drivers/fsi-master-acf/unbind
| ECPIX-5 | Lattice ECP5 | LFE5UM5G-85F | 75MHz | FTDI | 16-bit 512MB DDR3 | No | 1Gbps RGMII | 16MB QSPI | Yes | devmem 0x1e780024 32 0x00010000
| Fomu | Lattice iCE40 | iCE40-UP5K | 12MHz | USB | 128KB SPRAM | No | No | 16MB QSPI | No |
| HADBadge | Lattice ECP5 | LFE5U-45F | 48MHz | IOs | 8-bit 32MB SDR | No | No | 16MB QSPI | No | # Disable AST I2C bus 13 pins
| iCEBreaker | Lattice iCE40 | iCE40-UP5K | 24MHz | FTDI | 128KB SPRAM | No | No | 16MB QSPI | No | devmem 0x1e6e2090 32 0x023f0000
| LogicBone | Lattice ECP5 | LFE5U-45F | 75MHz | FTDI | 16-bit 1GB DDR3 | No | 1Gbps RGMII | 16MB QSPI | Yes |
| MarbleMini | Xilinx Artix7 | XC7A100T | 100MHz | FTDI | 16-bit 1GB DDR3 | No | 1Gbps RGMII | 16MB QSPI | No | ## All hosts
| MiniSpartan6 | Xilinx Spartan6 | XC6SLX25 | 80MHz | FTDI | 16-bit 32MB SDR | No | No | 8MB QSPI | Yes | Most, if not all, mainboards will require some form of storage for the bootloader and platform firmware. Kestrel contains a high-speed SPI/QSPI master that can be used to attach any standard SPI Flash device. We recommend that all wires be kept as short as possible between the Versa board and the external SPI device to minimize interference and maximize transfer rates.
| NeTV2 | Xilinx Artix7 | XC7A35T | 100MHz | IOs | 32-bit 512MB DDR3 | Gen2 X4 | 100Mbps RMII | 16MB QSPI | Yes |
| OrangeCrab | Lattice ECP5 | LFE5U-25F | 48MHz | USB | 16-bit 128MB SDR | No | No | 4MB QSPI | Yes | We strongly recommend you reference the pin configuration file at litex-boards/litex_boards/platforms/versa_ecp5.py when attaching any devices or external mainboards to the Versa board. This file contains the pin information that will, in conjunction with the Versa board schematics, allow correct wiring of the ECP5 to any attached hardware.
| Pipistrello | Xilinx Spartan6 | XC6SLX45 | 83MHz | FTDI | 16-bit 64MB LPDDR | No | No | 16MB QSPI | Yes* |
| ULX3S | Lattice ECP5 | LFE5U-45F | 50MHz | FTDI | 16-bit 32MB SDR | No | No | 4MB QSPI | Yes | # How to use
| TrellisBoard | Lattice ECP5 | LFE5UM5G-85F | 75MHz | FTDI | 32-bit 1GB DDR3 | Gen2 X1* | 1Gbps RGMII | 16MB QSPI | Yes |
| TinyFPGA | Lattice iCE40 | iCE40-LP8K | 16MHz | IOs | No | No | No | 16MB QSPI | No | ## Overview
Due to FPGA size constraints on the Versa board, host I/O and control is limited to a serial console at this time. Ethernet and automatic BMC firmware loading support, while entirely possible from a logical standpoint, will require either further Microwatt size optimization to free up resources on the ECP5 -45 FPGA used on the Versa board, or the use of a larger ECP5 device (see the Future Direction section for more details).
\* Present on the board but not yet supported or validated with LiteX.
## Bitstream and firmware load
[> Accelerator boards In most test and development applications, the soft BMC firmware will be loaded from the same host machine that is loading the ECP5 bitstream to the target board. Consistent with the build process, we use POWER hosts to load and control the ECP5 during development. If desired, it is also possible to flash the FPGA bitstream and BMC firmware to the on-board Flash memory of the Versa board, although that process is highly board-specific and is outside the intended scope of this document.
---------------------
The recommended test setup is two console windows, one running the LiteX terminal and firmware loader on the target's FTDI serial interface:
PCIe accelerators boards that you could use to accelerate your applications, LiteX provides you the essential cores for it: LitePCIe and LiteDRAM along with the LiteX infrastructure to create a design and easily control it/debug it.
cd kestrel/litex/litex-boards/litex_boards/targets/firmware
| Name | FPGA Family | FPGA device | Sys-Clk | TTY | DRAM | PCIe | Flash | make
|----------------|---------------------|---------------|----------|------|-----------------------|---------------|-------------| python3 kestrel/litex/litex/litex/tools/litex_term.py --speed 115200 /dev/ttyUSB1 --kernel kestrel/litex/litex-boards/litex_boards/targets/firmware/firmware.bin
| AcornCLE215+ | Xilinx Artix7 | XC7A200T | 125MHz | PCIe | 16-bit 1GB DDR3 | Gen2 X4 | 16MB QSPI |
| ForestKitten33 | Xilinx Ultrascale+ | XCVU33P | 125MHz | PCIe | 2 x 1024-bit 4GB HBM2*| Gen3 X16 | ? | and the other running the OpenOCD programming tool:
| BCU1525 | Xilinx Ultrascale+ | XCVU9P | 125MHz | PCIe | 4 x 64-bit DDR4 DIMM | Gen3 X16 | ? |
| AlveoU250 | Xilinx Ultrascale+ | XCU250 | 125MHz | PCIe | 4 x 64-bit DDR4 DIMM | Gen2 X16 | ? | cd kestrel/litex/litex-boards/litex_boards/targets
| AlveoU280 | Xilinx Ultrascale+ | XCU280 | 125MHz | PCIe* | 2 x 64-bit DDR4 DIMM* & HBM2* | Gen2 X16 | ? | openocd --log_output openocd.log 3 -f "/usr/share/trellis/misc/openocd/ecp5-versa.cfg" -c "transport select jtag; init; svf build/versa_ecp5/gateware/versa_ecp5.svf; exit"
\* Present on the board but not yet supported or validated with LiteX. When it is desired to recompile the firmware and re-upload, exit the LiteX terminal with a rapid `Ctrl+C Ctrl+C`, re-run make in the firmware directory, and then restart the LiteX terminal. From there, you may either us the `reboot` command at the BMC terminal, or re-run OpenOCD to reset all hardware inside the FPGA with a new bistream load.
[> Repurposed hardware ## Host control and initial IPL
---------------------- When the Kestrel firmware finishes loading the PNOR image from external Flash memory and completes its self-checks, a `FSP0>` prompt will appear on the serial console. From this prompt, several commands are supported. The most commonly used command is `poweron`, it will power on the board, start the IPL process, and attach a host serial console. To escape the host serial console, the standard `~.<RETURN>` escape sequence is supported. `chassisoff` will power down the host immediately. Other supported commands are listed in the built-in help system, which is available with the `help` command.
Repurposed FPGA hardware that has been "documented" by enthusiasts :), allows you to discover FPGAs for very cheap (starting at 15$)! ## Example console output
| Name | FPGA Family | FPGA device | Sys-Clk | TTY | DRAM | Ethernet | Flash | If you've wired everything up correctly, and depending on exactly how your host POWER9 system's PNOR was configured along with the debug options active on the Kestrel BMC, you should see output similar to the following upon issuing the `poweron` command at the Kestrel console:
|--------------|---------------------|---------------|----------|------|--------------------|--------------------|-------------|
| SDS1104X-E | Xilinx Zynq | XC7Z020 | 100MHz | Eth | 32-bit 256MB DDR3 | 100Mbps MII | ? | FSP0>poweron
| Colorlight5A | Lattice ECP5 | LFE5U-25F | 60MHz | IOs | 32-bit 8MB SDR | 2x 1Gbps RGMII | 4MB QSPI | Platform FPGA communication verified
| Linsn RV901 | Xilinx Spartan6 | XC6SLX16 | 75MHz | IOs | 32-bit 8MB SDR | 2x 1Gbps RGMII | 4MB QSPI | Commanding chassis power ON...
| PanoLogic G2 | Xilinx Spartan6 | XC6SLX100-150 | 50MHz | IOs | 32-bit 128MB DDR2 | 1Gbps GMII | 16MB QSPI | Chassis power verified active
| Camlink-4K | Lattice ECP5 | LFE5U-25F | 81MHz | IOs | 16-bit 128MB DDR3 | No | ?MB QSPI | 1 CPU(s) installed
Applying AVSBus workarounds...
The Colorlight5A is a very nice board to start with, cheap, powerful, easy to use with the open-source toolchain, you can find a specific LiteX project [here](https://github.com/enjoy-digital/colorlite) VDD/VCS 0: Enabling AVSBus CLK/MDAT pullups and selecting VIH/VIL 0x2 (0.65V/0.55V)
VDN 0: Enabling AVSBus CLK/MDAT pullups and selecting VIH/VIL 0x2 (0.65V/0.55V)
\* Present on the board but not yet supported or validated with LiteX. AVSBus workaround application complete!
Enabling AVSbus PMBUS functionality...
[> Development boards VDD 0: Placing device in AVSBus voltage command mode
--------------------- VCS 0: Placing device in AVSBus voltage command mode
VDN 0: Placing device in AVSBus voltage command mode
| Name | FPGA Family | FPGA device | Sys-Clk | TTY | RAM | PCIe | Ethernet | Flash | SDCard | AVSBus PMBUS functionality enabled!
|--------------|---------------------|---------------|---------|------|--------------------|-----------|----------------|-------------|--------| initialize_fsi_master(): after setup: ctl 0x00031400, sta 0x10000000
| AC701 | Xilinx Artix7 | XC7A200T | 100MHz | FTDI | 64-bit ?MB DDR3 | Gen2 X4 | 1Gbps RGMII | 16MB QSPI | Yes* | Starting IPL on side 0
| Aller | Xilinx Artix7 | XC7A200T | 100MHz | PCIe | 16-bit 256MB DDR3 | Gen2 X4 | No | 128MB QSPI | No | access_fsi_mem(): address 0x000800, data: 0xa0ff0800 sta: 0x41000001
| Arty(A7) | Xilinx Artix7 | XC7A35T | 100MHz | FTDI | 16-bit 256MB DDR3 | No | 100Mbps MII | 16MB QSPI | No | access_fsi_mem(): address 0x000900, data: 0x00000001 sta: 0x41000001
| ArtyS7 | Xilinx Spartan7 | XC7S50 | 100MHz | FTDI | 16-bit 256MB DDR3 | No | No | 16MB QSPI | No | access_fsi_mem(): address 0x000900, data: 0x00000001 sta: 0x41000001
| Avalanche | Microsemi PolarFire | MPF300TS | 100MHz | IOs | 16-bit 256MB DDR3 | No | 1Gbps RGMII* | 8MB QSPI* | No | access_fsi_mem(): address 0x000900, data: 0x00000001 sta: 0x41000001
| C10LPRefKit | Intel Cyclone10 | 10CL055 | 50MHz | FTDI | 16-bit 32MB SDR | No | 100Mbps MII | 16MB QSPI | No | access_fsi_mem(): address 0x002824, data: 0x00000000 sta: 0x41000001
| De0Nano | Intel Cyclone4 | EP4CE22F | 50MHz | FTDI | 16-bit 32MB SDR | No | No | No | No | access_fsi_mem(): address 0x000808, data: 0x02040000 sta: 0x41000001
| De10Lite | Intel MAX10 | 10M50DA | 50MHz | IOs | 16-bit 64MB SDR | No | No | No | No | access_fsi_mem(): address 0x000814, data: 0x04000510 sta: 0x41000001
| DECA | Intel MAX10 | 10M50DA | 50MHz | JTAG | 16-bit 512MB DDR3* | No | Yes | No | Yes | access_fsi_mem(): address 0x000808, data: 0x02040000 sta: 0x41000001
| De10Nano | Intel Cyclone5 | 5CSEBA6 | 50MHz | IOs | 16-bit 32MB SDR | No | No | No | Yes | access_fsi_mem(): address 0x000900, data: 0x00000001 sta: 0x41000001
| Arrow SoCKit | Intel Cyclone5 | 5CSXFC6D6F31C8| 50MHz | JTAG | 32-bit 1GB DDR3* | No | No | No | No | access_fsi_mem(): address 0x002c60, data: 0xeeeef304 sta: 0x41000001
| De1SoC | Intel Cyclone5 | 5CSEMA5 | 50MHz | IOs | 16-bit 64MB SDR | No | ? | ? | ? | access_fsi_mem(): address 0x002c60, data: 0xeeeef30c sta: 0x41000001
| De2-115 | Intel Cyclone4 | EP4CE115 | 50MHz | IOs | 16-bit 128MB SDR | No | 1Gbps GMII* | 8MB QSPI | Yes* | access_fsi_mem(): address 0x000870, data: 0x20000000 sta: 0x41000001
| ECP5-EVN | Lattice ECP5 | LFE5UM5G-85F | 50MHz | FTDI | No | No | ? | ? | ? | access_fsi_mem(): address 0x001034, data: 0x60000000 sta: 0x41000001
| Genesys2 | Xilinx Kintex7 | XC7K325T | 125MHz | FTDI | 32-bit 1GB DDR3 | No | 1Gbps RGMII | 32MB QSPI* | Yes | access_fsi_mem(): address 0x00102c, data: 0xffffffff sta: 0x41000001
| KC705 | Xilinx Kintex7 | XC7K325T | 125MHz | FTDI | 64-bit 1GB DDR3 | Gen2 X8** | 1Gbps GMII | 32MB QSPI* | Yes | access_fsi_mem(): address 0x002820, data: 0x00000000 sta: 0x41000001
| KCU105 | Xilinx KintexU | XCKU40 | 125MHz | FTDI | 64-bit 1GB DDR4 | Gen3 X8** | 1Gbps-BASE-X | 64MB QSPI* | Yes | access_fsi_mem(): address 0x002820, data: 0x00000000 sta: 0x41000001
| KX2 | Xilinx Kintex7 | XC7K160T | 125MHz | FTDI | 64-bit 1GB DDR3 | No | No | 64MB QSPI* | No | access_fsi_mem(): address 0x002804, data: 0x04c04000 sta: 0x41000001
| LiteFury | Xilinx Artix7 | XC7A100T | 100MHz | PCIe | 16-bit 512MB DDR3 | Gen2 X4 | No | 32MB QSPI* | No | access_fsi_mem(): address 0x002804, data: 0x04c04000 sta: 0x41000001
| MachXO3 | Lattice MachXO3 | LCMXO3L-6900C | 125MHz | ? | ? | No | No | ? | No | access_fsi_mem(): address 0x002804, data: 0x84c04000 sta: 0x41000001
| Mercury XU5 | Xilinx ZynqU+ | XCZU2EG | 125MHz | FTDI | 16-bit 512MB DDR4 | No | No | 64MB QSPI* | No |
| Mimas A7 | Xilinx Artix7 | XC7A50T | 100MHz | FTDI | 16-bit 256MB DDR3 | No | 1Gbps RGMII | 16MB QSPI | No | --== Welcome to SBE - CommitId[0x9cc77bc5] ==--
| Nereid | Xilinx Kintex7 | XC7K160T | 100MHz | PCIe | 64-bit 4GB DDR3 | Gen2 X4 | No | 16MB QSPI | No | SBE starting hostboot
| Nexys4DDR | Xilinx Artix7 | XC7A100T | 100MHz | FTDI | 16-bit 128MB DDR2 | No | 100Mbps RMII | 16MB QSPI* | Yes |
| Nexys Video | Xilinx Artix7 | XC7A200T | 100MHz | FTDI | 16-bit 512MB DDR3 | No | 1Gbps RMII | 32MB QSPI* | Yes | --== Welcome to Hostboot hostboot-8f8fa4c/hbicore.bin ==--
| SP605 | Xilinx Spartan6 | XC6SLX45T | 100MHz | FTDI | 16-bit 128MB DDR3* | Gen1 X1* | 1Gbps GMII | 8MB QSPI* | Yes* |
| Tagus | Xilinx Artix7 | XC7A200T | 100MHz | PCIe | 16-bit 256MB DDR3 | Gen2 X1 | 1Gbps-BASE-X* | 16MB QSPI* | No | Note the FSI start sequence is the last task to run after main platform setup and that the console switches over to the host console directly afterward. If you see no output past that point, there is likely an issue with the LPC or SPI PNOR bus wiring. Alternately, it is possible the SPI PNOR device does not contain a useable firmware image. Debug information in this situation can be obtained by escaping to the Kestrel console and running the `sbe_status` command.
| VC707 | Xilinx Virex7 | XC7VX485T | 125MHz | FTDI | 64-bit 1GB DDR3 | Gen3 X8* | 1Gbps GMII | 16MB QSPI* | Yes* |
| VCU118 | Xilinx VirtexU+ | XCVU9P | 125MHz | FTDI | 2 x 64-bit 4GB DDR4| Gen3 X16*| 1Gbps SGMII | 16MB QSPI* | Yes* | # Status
| Versa ECP5 | Lattice ECP5 | LFE5UM5G-45F | 75MHz | FTDI | 16-bit 128MB DDR3 | Gen1 X1* | 1Gbps RGMII | 16MB QSPI* | No |
| ZCU104 | Xilinx ZynqU+ | XCZU7EV | 125MHz | FTDI | 64-bit 1GB DDR4 | No | 1Gbps RGMII* | 64MB QSPI* | Yes* | ## Known Issues
| Zybo Z7 | Xilinx ZynqU+ | XC7Z010 | 125MHz | FTDI | 64-bit 1GB DDR4 | No | 1Gbps RGMII* | 64MB QSPI* | Yes* |
- Many IPMI commands are unimplemented in this initial release, causing the OCCs to fail to come online [^2] [^3]. These commands will be implemented over the coming weeks and months.
\* Present on the board but not yet supported or validated with LiteX. - NextPNR continues to indicate timing failure even though the design operates as intended. This needs to be investigated and resolved.
- Microwatt is consuming around half of the entire FPGA on the Versa ECP5 -45 devices. This is due to issues within GHDL/Yosys/NextPNR, apparently triggered by the Microwatt codebase, that need to be investigated and resolved.
## Future Direction
Kestrel is an active development project at Raptor Engineering, and as such features will continue to be implemented over time. Our current focus is the remaining IPMI commands, followed by Microwatt size reduction in an effort to (re)enable Ethernet support. Linux is also on our roadmap, although timing is currently unknown due to the aforementioned blocking factors.
Kestrel is intended to be used on an upcoming Raptor Computing Systems product incorporating a much larger ECP5 FPGA. This product is not a standard PC form factor device, nor will it be a cost focused product, but it is designed partly as a development platform for Kestrel technologies. Look for more information on this specialty product later in 2021!
# Licensing
Raptor Engineering has made the Kestrel project specific HDL and firmware open to the public under the GPL v3. Should you require other licensing terms, we are able to extend a commercial license of the codebase as needed. Please contact sales@raptorengineering.com for more information and pricing details.
We welcome contributions and enhancements to Kestrel. Due to the use of BSD and GPL licenses throughout the various Kestrel sub-repsitories, we may be able to merge pull requests for some modules without a CLA, while we may require a CLA for modifications to other modules. We will make any CLA requirements clear in pull request comments, but as a general rule the Raptor GPL-licensed modules will require a CLA for contributions to be upstreamed.
[^1]: https://www.raptorcs.com
[^2]: Minimum to IPL IPMI commands have been documented here: https://wiki.raptorcs.com/wiki/OpenBMC/StepsToIPL#Needed_non-openbmc_programs
[^3]: A sample of one command know to block OCC onlining (written in C) is here: https://gitlab.raptorengineering.com/bangbmc-firmware/ipmi-grpext-dcmi/-/blob/raw-first-pass/src/lib/grpext-dcmi.c
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