Commit 5fbb176c authored by Florent Kermarrec's avatar Florent Kermarrec

targets/crosslink_nx: update NXLRAM import.

parent afe44e2b
...@@ -15,7 +15,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer ...@@ -15,7 +15,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import crosslink_nx_evn from litex_boards.platforms import crosslink_nx_evn
from litex.soc.cores.nxlram import NXLRAM from litex.soc.cores.ram import NXLRAM
from litex.soc.cores.clock import NXPLL from litex.soc.cores.clock import NXPLL
from litex.soc.cores.spi_flash import SpiFlash from litex.soc.cores.spi_flash import SpiFlash
from litex.build.io import CRG from litex.build.io import CRG
......
...@@ -21,7 +21,7 @@ from litex_boards.platforms import crosslink_nx_vip ...@@ -21,7 +21,7 @@ from litex_boards.platforms import crosslink_nx_vip
from litehyperbus.core.hyperbus import HyperRAM from litehyperbus.core.hyperbus import HyperRAM
from litex.soc.cores.nxlram import NXLRAM from litex.soc.cores.ram import NXLRAM
from litex.soc.cores.spi_flash import SpiFlash from litex.soc.cores.spi_flash import SpiFlash
from litex.build.io import CRG from litex.build.io import CRG
from litex.build.generic_platform import * from litex.build.generic_platform import *
......
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