diff --git a/litex_boards/targets/crosslink_nx_evn.py b/litex_boards/targets/crosslink_nx_evn.py
index 350c64790d04f20357990395ce2c56bf26900b46..e7396525066a55dac03a3eab640b2e3d41f0e4bb 100755
--- a/litex_boards/targets/crosslink_nx_evn.py
+++ b/litex_boards/targets/crosslink_nx_evn.py
@@ -15,7 +15,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from litex_boards.platforms import crosslink_nx_evn
 
-from litex.soc.cores.nxlram import NXLRAM
+from litex.soc.cores.ram import NXLRAM
 from litex.soc.cores.clock import NXPLL
 from litex.soc.cores.spi_flash import SpiFlash
 from litex.build.io import CRG
diff --git a/litex_boards/targets/crosslink_nx_vip.py b/litex_boards/targets/crosslink_nx_vip.py
index 1da6c5bbd78b69ee342f8aef571014e1123cc43e..fa032ff5ae4c488b824c38a98c78e1bb20a66183 100755
--- a/litex_boards/targets/crosslink_nx_vip.py
+++ b/litex_boards/targets/crosslink_nx_vip.py
@@ -21,7 +21,7 @@ from litex_boards.platforms import crosslink_nx_vip
 
 from litehyperbus.core.hyperbus import HyperRAM
 
-from litex.soc.cores.nxlram import NXLRAM
+from litex.soc.cores.ram import NXLRAM
 from litex.soc.cores.spi_flash import SpiFlash
 from litex.build.io import CRG
 from litex.build.generic_platform import *