orangecrab: Run reset_timer with por/48MHz clock domain (sys clock domain is...

orangecrab: Run reset_timer with por/48MHz clock domain (sys clock domain is now directly reseted on usr_btn press).

litex_boards/targets/orangecrab.py

@@ -66,7 +66,8 @@ class _CRG(Module):
             usb_pll.create_clkout(self.cd_usb_12, 12e6)
 
         # FPGA Reset (press usr_btn for 1 second to fallback to bootloader)
-        reset_timer = WaitTimer(sys_clk_freq)
+        reset_timer = WaitTimer(int(48e6))
+        reset_timer = ClockDomainsRenamer("por")(reset_timer)
         self.submodules += reset_timer
         self.comb += reset_timer.wait.eq(~rst_n)
         self.comb += platform.request("rst_n").eq(~reset_timer.done)
@@ -83,7 +84,6 @@ class _CRGSDRAM(Module):
 
         # # #
 
-
         self.stop  = Signal()
         self.reset = Signal()
 
@@ -136,7 +136,8 @@ class _CRGSDRAM(Module):
             usb_pll.create_clkout(self.cd_usb_12, 12e6)
 
         # FPGA Reset (press usr_btn for 1 second to fallback to bootloader)
-        reset_timer = WaitTimer(sys_clk_freq)
+        reset_timer = WaitTimer(int(48e6))
+        reset_timer = ClockDomainsRenamer("por")(reset_timer)
         self.submodules += reset_timer
         self.comb += reset_timer.wait.eq(~rst_n)
         self.comb += platform.request("rst_n").eq(~reset_timer.done)