Remove the LiteX timer peripheral

The LiteX timer peripheral wastes resources and is not required
for operation of the BIOS on POWER SoCs.

README.md

@@ -32,7 +32,7 @@ Building the Kestrel BMC for the ECP-5 FPGA on the Versa board is quite straight
 Please see the [Quick Start Guide](https://gitlab.raptorengineering.com/kestrel-collaboration/kestrel-litex/litex/-/wikis/Quick-Start) for setup instructions applicable to the standard Raptor development environment on POWER9.  After the subrepositories are set up, simply run:
 
     cd kestrel/litex/litex-boards/litex_boards/targets
-    ./versa_ecp5.py --device=LFE5UM --cpu-type=microwatt --cpu-variant=standard+ghdl+irq --with-ethernet --build --nextpnr-seed 1
+    ./versa_ecp5.py --device=LFE5UM --cpu-type=microwatt --cpu-variant=standard+ghdl+irq --with-ethernet --build --nextpnr-seed 4
 
 # Updating the bitstream with new firmware
 

litex_boards/targets/versa_ecp5.py

@@ -129,12 +129,11 @@ class BaseSoC(SoCCore):
         kwargs["csr_data_width"] = 8
         kwargs["csr_paging"] = 0x800
 
-        # Disable timer uptime counter
-        # Microwatt already provides an architecturally-defined timer with interrupt (decrementer),
+        # Disable timer peripheral
+        # Microwatt, or any other POWER-compliant CPU, already provides an
+        # architecturally-defined timer with interrupt (decrementer),
         # so the LiteX one just wastes resources in Kestrel.
-        # FIXME: The entire timer could be removed if the LiteX BIOS could make use of the POWER decrementer,
-        # freeing resources for something else.
-        kwargs["with_timer"] = True
+        kwargs["with_timer"] = False
         kwargs["timer_uptime"] = False
 
         # FIXME: adapt integrated rom size for Microwatt