Configure Lattice SPI master into high speed mode

This reduces FPGA bitstream load time from Flash well below
1 second.

Thanks to mithro for the pointer to the ECP5 bistream packer
options!
parent f804d87b
...@@ -455,6 +455,9 @@ def main(): ...@@ -455,6 +455,9 @@ def main():
os.path.join(builder.gateware_dir, soc.platform.name + "_stuffed.config"), os.path.join(builder.gateware_dir, soc.platform.name + "_stuffed.config"),
"--svf", os.path.join(builder.gateware_dir, soc.platform.name + ".svf"), "--svf", os.path.join(builder.gateware_dir, soc.platform.name + ".svf"),
"--bit", os.path.join(builder.gateware_dir, soc.platform.name + ".bit"), "--bit", os.path.join(builder.gateware_dir, soc.platform.name + ".bit"),
"--spimode", "fast-read",
"--freq", "38.8",
"--compress",
"--bootaddr", "0"]) "--bootaddr", "0"])
if args.load: if args.load:
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment