Configure Lattice SPI master into high speed mode

This reduces FPGA bitstream load time from Flash well below
1 second.

Thanks to mithro for the pointer to the ECP5 bistream packer
options!

litex_boards/targets/versa_ecp5.py

@@ -455,6 +455,9 @@ def main():
                         os.path.join(builder.gateware_dir, soc.platform.name + "_stuffed.config"),
                         "--svf", os.path.join(builder.gateware_dir, soc.platform.name + ".svf"),
                         "--bit", os.path.join(builder.gateware_dir, soc.platform.name + ".bit"),
+                        "--spimode", "fast-read",
+                        "--freq", "38.8",
+                        "--compress",
                         "--bootaddr", "0"])
 
     if args.load: