From 54102b7c2f1b8cd7430d36f7599ba2ab9dfa8607 Mon Sep 17 00:00:00 2001 From: Raptor Engineering Development Team Date: Thu, 29 Apr 2021 14:12:44 -0500 Subject: [PATCH] Configure Lattice SPI master into high speed mode This reduces FPGA bitstream load time from Flash well below 1 second. Thanks to mithro for the pointer to the ECP5 bistream packer options! --- litex_boards/targets/versa_ecp5.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/litex_boards/targets/versa_ecp5.py b/litex_boards/targets/versa_ecp5.py index a4ab405..2cdbb50 100755 --- a/litex_boards/targets/versa_ecp5.py +++ b/litex_boards/targets/versa_ecp5.py @@ -455,6 +455,9 @@ def main(): os.path.join(builder.gateware_dir, soc.platform.name + "_stuffed.config"), "--svf", os.path.join(builder.gateware_dir, soc.platform.name + ".svf"), "--bit", os.path.join(builder.gateware_dir, soc.platform.name + ".bit"), + "--spimode", "fast-read", + "--freq", "38.8", + "--compress", "--bootaddr", "0"]) if args.load: -- 2.30.2