deca: Integrate Video Terminal (untested, resource issue).

litex_boards/platforms/deca.py

@@ -199,14 +199,14 @@ _io = [
 
     # HDMI
     ("hdmi", 0,
-        Subsignal("tx_d_r", Pins("C18 D17 C17 C19 D14 B19 D13 A19 C14")),
-        Subsignal("tx_d_g", Pins("C14 A17 B16 C15 A14 A15 A12 A16")),
-        Subsignal("tx_d_b", Pins("A13 C16 C12 B17 B12 B14 A18 C13")),
-        Subsignal("tx_clk", Pins("A20")),
-        Subsignal("tx_de",  Pins("C9")),
-        Subsignal("tx_hs",  Pins("B11")),
-        Subsignal("tx_vs",  Pins("C11")),
-        Subsignal("tx_int", Pins("B10")),
+        Subsignal("r", Pins("C18 D17 C17 C19 D14 B19 D13 A19")),
+        Subsignal("g", Pins("C14 A17 B16 C15 A14 A15 A12 A16")),
+        Subsignal("b", Pins("A13 C16 C12 B17 B12 B14 A18 C13")),
+        Subsignal("clk",   Pins("A20")),
+        Subsignal("de",    Pins("C9")),
+        Subsignal("hsync", Pins("B11")),
+        Subsignal("vsync", Pins("C11")),
+        Subsignal("int",   Pins("B10")),
         Misc("FAST_OUTPUT_REGISTER ON"),
         IOStandard("1.8 V")
     ),

litex_boards/targets/deca.py

@@ -21,6 +21,7 @@ from litex.soc.integration.soc import SoCRegion
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
+from litex.soc.cores.video import VideoDVIPHY
 from litex.soc.cores.led import LedChaser
 
 # CRG ----------------------------------------------------------------------------------------------
@@ -29,7 +30,7 @@ class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
         self.rst = Signal()
         self.clock_domains.cd_sys    = ClockDomain()
-        self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
+        self.clock_domains.cd_hdmi   = ClockDomain()
 
         # # #
 
@@ -41,12 +42,12 @@ class _CRG(Module):
         self.comb += pll.reset.eq(self.rst)
         pll.register_clkin(clk50, 50e6)
         pll.create_clkout(self.cd_sys,  sys_clk_freq)
-        pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
+        pll.create_clkout(self.cd_hdmi, 40e6)
 
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(50e6), with_vga=False, **kwargs):
+    def __init__(self, sys_clk_freq=int(50e6), with_video_terminal=False, **kwargs):
         platform = deca.Platform()
 
         # Defaults to UART over JTAG because no hardware uart is on the board
@@ -62,6 +63,11 @@ class BaseSoC(SoCCore):
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
 
+        # Video ------------------------------------------------------------------------------------
+        if with_video_terminal:
+            self.submodules.videophy = VideoDVIPHY(platform.request("hdmi"), clock_domain="hdmi")
+            self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
+
         # Leds -------------------------------------------------------------------------------------
         self.submodules.leds = LedChaser(
             pads         = platform.request_all("user_led"),
@@ -75,12 +81,14 @@ def main():
     parser.add_argument("--build",               action="store_true", help="Build bitstream")
     parser.add_argument("--load",                action="store_true", help="Load bitstream")
     parser.add_argument("--sys-clk-freq",        default=50e6,        help="System clock frequency (default: 50MHz)")
+    parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA)")
     builder_args(parser)
     soc_sdram_args(parser)
     args = parser.parse_args()
 
     soc = BaseSoC(
         sys_clk_freq        = int(float(args.sys_clk_freq)),
+        with_video_terminal = args.with_video_terminal,
         **soc_sdram_argdict(args)
     )
     builder = Builder(soc, **builder_argdict(args))