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Kestrel Collaboration
Kestrel LiteX
litex-boards
Commits
46e8a957
Commit
46e8a957
authored
Nov 12, 2020
by
Florent Kermarrec
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platforms/zybo_z7: fix default_clk typo.
parent
ac075f18
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litex_boards/platforms/zybo_z7.py
litex_boards/platforms/zybo_z7.py
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litex_boards/platforms/zybo_z7.py
View file @
46e8a957
...
...
@@ -89,7 +89,7 @@ _connectors = [
# Platform -----------------------------------------------------------------------------------------
class
Platform
(
XilinxPlatform
):
default_clk_name
=
"clk12
8
"
default_clk_name
=
"clk12
5
"
default_clk_period
=
1e9
/
125e6
def
__init__
(
self
):
...
...
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