From 3e3c233c415a1edd9a8f92591f4aa61fd11d5698 Mon Sep 17 00:00:00 2001 From: Raptor Engineering Development Team Date: Fri, 26 Mar 2021 15:10:37 -0500 Subject: [PATCH] Reduce clock rate from 75MHz to 50MHz to avoid incorrect CPU operation under Linux --- litex_boards/targets/versa_ecp5.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_boards/targets/versa_ecp5.py b/litex_boards/targets/versa_ecp5.py index 83ce813..6c182ef 100755 --- a/litex_boards/targets/versa_ecp5.py +++ b/litex_boards/targets/versa_ecp5.py @@ -369,7 +369,7 @@ def main(): parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain: trellis (default) or diamond") - parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)") + parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)") parser.add_argument("--device", default="LFE5UM5G", help="FPGA device (LFE5UM5G (default) or LFE5UM)") ethopts = parser.add_mutually_exclusive_group() ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") -- 2.30.2