diff --git a/litex_boards/targets/versa_ecp5.py b/litex_boards/targets/versa_ecp5.py
index 83ce81396d6396ee3c44568562df45a6e2ea0493..6c182ef0d9e3a46a6a23c91713c2c8c2c801e281 100755
--- a/litex_boards/targets/versa_ecp5.py
+++ b/litex_boards/targets/versa_ecp5.py
@@ -369,7 +369,7 @@ def main():
     parser.add_argument("--build",           action="store_true",              help="Build bitstream")
     parser.add_argument("--load",            action="store_true",              help="Load bitstream")
     parser.add_argument("--toolchain",       default="trellis",                help="FPGA toolchain: trellis (default) or diamond")
-    parser.add_argument("--sys-clk-freq",    default=75e6,                     help="System clock frequency (default: 75MHz)")
+    parser.add_argument("--sys-clk-freq",    default=50e6,                     help="System clock frequency (default: 50MHz)")
     parser.add_argument("--device",          default="LFE5UM5G",               help="FPGA device (LFE5UM5G (default) or LFE5UM)")
     ethopts = parser.add_mutually_exclusive_group()
     ethopts.add_argument("--with-ethernet",  action="store_true",              help="Enable Ethernet support")