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Kestrel Collaboration
Kestrel LiteX
litex-boards
Commits
36b7fb10
Unverified
Commit
36b7fb10
authored
Dec 21, 2020
by
enjoy-digital
Committed by
GitHub
Dec 21, 2020
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Merge pull request #134 from Disasm/fix-orangecrab
Fix FPGA reset logic for orangecrab target
parents
e1f9fd1a
f6a106cd
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litex_boards/targets/orangecrab.py
litex_boards/targets/orangecrab.py
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litex_boards/targets/orangecrab.py
View file @
36b7fb10
...
...
@@ -69,7 +69,7 @@ class _CRG(Module):
reset_timer
=
WaitTimer
(
sys_clk_freq
)
self
.
submodules
+=
reset_timer
self
.
comb
+=
reset_timer
.
wait
.
eq
(
~
rst_n
)
self
.
comb
+=
platform
.
request
(
"rst_n"
).
eq
(
reset_timer
.
done
)
self
.
comb
+=
platform
.
request
(
"rst_n"
).
eq
(
~
reset_timer
.
done
)
class
_CRGSDRAM
(
Module
):
...
...
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