Merge pull request #134 from Disasm/fix-orangecrab

Fix FPGA reset logic for orangecrab target

Merge pull request #134 from Disasm/fix-orangecrab
Fix FPGA reset logic for orangecrab target
36b7fb10 · enjoy-digital · GitHub · e1f9fd1a · f6a106cd · 36b7fb10
Unverified Commit 36b7fb10 authored Dec 21, 2020 by enjoy-digital Committed by GitHub Dec 21, 2020
Hide whitespace changes
Inline Side-by-side

Showing with 1 addition and 1 deletion

litex_boards/targets/orangecrab.py litex_boards/targets/orangecrab.py +1 -1

No files found.
--- a/litex_boards/targets/orangecrab.py
+++ b/litex_boards/targets/orangecrab.py
@@ -69,7 +69,7 @@ class _CRG(Module):
        reset_timer = WaitTimer(sys_clk_freq)
        self.submodules += reset_timer
        self.comb += reset_timer.wait.eq(~rst_n)
-        self.comb += platform.request("rst_n").eq(reset_timer.done)
+        self.comb += platform.request("rst_n").eq(~reset_timer.done)


 class _CRGSDRAM(Module):