Unverified Commit 36b7fb10 authored by enjoy-digital's avatar enjoy-digital Committed by GitHub

Merge pull request #134 from Disasm/fix-orangecrab

Fix FPGA reset logic for orangecrab target
parents e1f9fd1a f6a106cd
......@@ -69,7 +69,7 @@ class _CRG(Module):
reset_timer = WaitTimer(sys_clk_freq)
self.submodules += reset_timer
self.comb += reset_timer.wait.eq(~rst_n)
self.comb += platform.request("rst_n").eq(reset_timer.done)
self.comb += platform.request("rst_n").eq(~reset_timer.done)
class _CRGSDRAM(Module):
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