Reduce resource wastage somewhat on newer LiteX versions

Successfully tested with all Kestrel peripherals and Ethernet enabled
parent 3e3c233c
......@@ -124,6 +124,9 @@ class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(50e6), device="LFE5UM5G", with_ethernet=False, with_etherbone=False, with_openfsi_master=True, with_hostspiflash=True, with_hostlpcslave=True, with_i2c_masters=True, with_simple_rtc=True, eth_ip="192.168.1.50", eth_phy=0, toolchain="trellis", **kwargs):
platform = versa_ecp5.Platform(toolchain=toolchain, device=device)
kwargs["csr_address_width"] = 14
kwargs["csr_data_width"] = 8
# FIXME: adapt integrated rom size for Microwatt
if kwargs.get("cpu_type", None) == "microwatt":
kwargs["integrated_rom_size"] = 0xd000 if with_ethernet else 0xb000
......@@ -141,7 +144,7 @@ class BaseSoC(SoCCore):
raise OSError("Kestrel HDL and firmware currently require a PowerPC-compatible CPU to function. Did you forget '--cpu-type=microwatt'?")
# SoCCore -----------------------------------------_----------------------------------------
SoCCore.__init__(self, platform, csr_data_width=32, irq_n_irqs=16, clk_freq=sys_clk_freq,
SoCCore.__init__(self, platform, irq_n_irqs=16, clk_freq=sys_clk_freq,
ident = "Kestrel SoC on Versa ECP5",
ident_version = True,
**kwargs)
......@@ -176,7 +179,7 @@ class BaseSoC(SoCCore):
rx_delay = 0e-9)
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
self.add_ethernet(phy=self.ethphy, dynamic_ip=False)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
......@@ -390,6 +393,7 @@ def main():
with_hostlpcslave = True,
with_openfsi_master = True,
with_i2c_masters = True,
with_simple_rtc = True,
eth_ip = args.eth_ip,
eth_phy = args.eth_phy,
toolchain = args.toolchain,
......
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