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Kestrel Collaboration
Kestrel LiteX
litex-boards
Commits
31e6997e
Commit
31e6997e
authored
Jul 01, 2020
by
Florent Kermarrec
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sdcard: rename cd_sdcard to cd_sd to avoid unnecessary clock domain.
parent
fe3ea805
Changes
6
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6 changed files
with
15 additions
and
15 deletions
+15
-15
litex_boards/targets/arty.py
litex_boards/targets/arty.py
+2
-2
litex_boards/targets/logicbone.py
litex_boards/targets/logicbone.py
+3
-3
litex_boards/targets/nexys4ddr.py
litex_boards/targets/nexys4ddr.py
+2
-2
litex_boards/targets/nexys_video.py
litex_boards/targets/nexys_video.py
+2
-2
litex_boards/targets/trellisboard.py
litex_boards/targets/trellisboard.py
+3
-3
litex_boards/targets/ulx3s.py
litex_boards/targets/ulx3s.py
+3
-3
No files found.
litex_boards/targets/arty.py
View file @
31e6997e
...
...
@@ -31,7 +31,7 @@ class _CRG(Module):
self
.
clock_domains
.
cd_sys4x_dqs
=
ClockDomain
(
reset_less
=
True
)
self
.
clock_domains
.
cd_clk200
=
ClockDomain
()
self
.
clock_domains
.
cd_eth
=
ClockDomain
()
self
.
clock_domains
.
cd_sd
card
=
ClockDomain
()
self
.
clock_domains
.
cd_sd
=
ClockDomain
()
# # #
...
...
@@ -43,7 +43,7 @@ class _CRG(Module):
pll
.
create_clkout
(
self
.
cd_sys4x_dqs
,
4
*
sys_clk_freq
,
phase
=
90
)
pll
.
create_clkout
(
self
.
cd_clk200
,
200e6
)
pll
.
create_clkout
(
self
.
cd_eth
,
25e6
)
pll
.
create_clkout
(
self
.
cd_sd
card
,
10e6
)
pll
.
create_clkout
(
self
.
cd_sd
,
10e6
)
self
.
submodules
.
idelayctrl
=
S7IDELAYCTRL
(
self
.
cd_clk200
)
...
...
litex_boards/targets/logicbone.py
View file @
31e6997e
...
...
@@ -33,7 +33,7 @@ class _CRG(Module):
self
.
clock_domains
.
cd_sys
=
ClockDomain
()
self
.
clock_domains
.
cd_sys2x
=
ClockDomain
()
self
.
clock_domains
.
cd_sys2x_i
=
ClockDomain
(
reset_less
=
True
)
self
.
clock_domains
.
cd_sd
card
=
ClockDomain
()
self
.
clock_domains
.
cd_sd
=
ClockDomain
()
# # #
...
...
@@ -57,7 +57,7 @@ class _CRG(Module):
pll
.
register_clkin
(
clk25
,
25e6
)
pll
.
create_clkout
(
self
.
cd_sys2x_i
,
2
*
sys_clk_freq
)
pll
.
create_clkout
(
self
.
cd_init
,
24e6
)
pll
.
create_clkout
(
self
.
cd_sd
card
,
10e6
)
pll
.
create_clkout
(
self
.
cd_sd
,
10e6
)
self
.
specials
+=
[
Instance
(
"ECLKBRIDGECS"
,
i_CLK0
=
self
.
cd_sys2x_i
.
clk
,
...
...
@@ -74,7 +74,7 @@ class _CRG(Module):
i_RST
=
self
.
reset
,
o_CDIVX
=
self
.
cd_sys
.
clk
),
AsyncResetSynchronizer
(
self
.
cd_init
,
~
por_done
|
~
pll
.
locked
),
AsyncResetSynchronizer
(
self
.
cd_sd
card
,
~
por_done
|
~
pll
.
locked
),
AsyncResetSynchronizer
(
self
.
cd_sd
,
~
por_done
|
~
pll
.
locked
),
AsyncResetSynchronizer
(
self
.
cd_sys
,
~
por_done
|
~
pll
.
locked
|
self
.
reset
),
AsyncResetSynchronizer
(
self
.
cd_sys2x
,
~
por_done
|
~
pll
.
locked
|
self
.
reset
),
]
...
...
litex_boards/targets/nexys4ddr.py
View file @
31e6997e
...
...
@@ -30,7 +30,7 @@ class _CRG(Module):
self
.
clock_domains
.
cd_sys2x_dqs
=
ClockDomain
(
reset_less
=
True
)
self
.
clock_domains
.
cd_clk200
=
ClockDomain
()
self
.
clock_domains
.
cd_eth
=
ClockDomain
()
self
.
clock_domains
.
cd_sd
card
=
ClockDomain
()
self
.
clock_domains
.
cd_sd
=
ClockDomain
()
# # #
...
...
@@ -42,7 +42,7 @@ class _CRG(Module):
pll
.
create_clkout
(
self
.
cd_sys2x_dqs
,
2
*
sys_clk_freq
,
phase
=
90
)
pll
.
create_clkout
(
self
.
cd_clk200
,
200e6
)
pll
.
create_clkout
(
self
.
cd_eth
,
50e6
)
pll
.
create_clkout
(
self
.
cd_sd
card
,
10e6
)
pll
.
create_clkout
(
self
.
cd_sd
,
10e6
)
self
.
submodules
.
idelayctrl
=
S7IDELAYCTRL
(
self
.
cd_clk200
)
...
...
litex_boards/targets/nexys_video.py
View file @
31e6997e
...
...
@@ -30,7 +30,7 @@ class _CRG(Module):
self
.
clock_domains
.
cd_sys4x_dqs
=
ClockDomain
(
reset_less
=
True
)
self
.
clock_domains
.
cd_clk200
=
ClockDomain
()
self
.
clock_domains
.
cd_clk100
=
ClockDomain
()
self
.
clock_domains
.
cd_sd
card
=
ClockDomain
()
self
.
clock_domains
.
cd_sd
=
ClockDomain
()
# # #
...
...
@@ -42,7 +42,7 @@ class _CRG(Module):
pll
.
create_clkout
(
self
.
cd_sys4x_dqs
,
4
*
sys_clk_freq
,
phase
=
90
)
pll
.
create_clkout
(
self
.
cd_clk200
,
200e6
)
pll
.
create_clkout
(
self
.
cd_clk100
,
100e6
)
pll
.
create_clkout
(
self
.
cd_sd
card
,
10e6
)
pll
.
create_clkout
(
self
.
cd_sd
,
10e6
)
self
.
submodules
.
idelayctrl
=
S7IDELAYCTRL
(
self
.
cd_clk200
)
...
...
litex_boards/targets/trellisboard.py
View file @
31e6997e
...
...
@@ -33,7 +33,7 @@ class _CRG(Module):
self
.
clock_domains
.
cd_sys
=
ClockDomain
()
self
.
clock_domains
.
cd_sys2x
=
ClockDomain
()
self
.
clock_domains
.
cd_sys2x_i
=
ClockDomain
(
reset_less
=
True
)
self
.
clock_domains
.
cd_sd
card
=
ClockDomain
()
self
.
clock_domains
.
cd_sd
=
ClockDomain
()
# # #
...
...
@@ -57,7 +57,7 @@ class _CRG(Module):
pll
.
register_clkin
(
clk12
,
12e6
)
pll
.
create_clkout
(
self
.
cd_sys2x_i
,
2
*
sys_clk_freq
)
pll
.
create_clkout
(
self
.
cd_init
,
25e6
)
pll
.
create_clkout
(
self
.
cd_sd
card
,
10
e6
)
pll
.
create_clkout
(
self
.
cd_sd
,
16
e6
)
self
.
specials
+=
[
Instance
(
"ECLKBRIDGECS"
,
i_CLK0
=
self
.
cd_sys2x_i
.
clk
,
...
...
@@ -75,7 +75,7 @@ class _CRG(Module):
i_RST
=
self
.
reset
,
o_CDIVX
=
self
.
cd_sys
.
clk
),
AsyncResetSynchronizer
(
self
.
cd_init
,
~
por_done
|
~
pll
.
locked
|
rst
),
AsyncResetSynchronizer
(
self
.
cd_sd
card
,
~
por_done
|
~
pll
.
locked
|
rst
),
AsyncResetSynchronizer
(
self
.
cd_sd
,
~
por_done
|
~
pll
.
locked
|
rst
),
AsyncResetSynchronizer
(
self
.
cd_sys
,
~
por_done
|
~
pll
.
locked
|
rst
|
self
.
reset
),
AsyncResetSynchronizer
(
self
.
cd_sys2x
,
~
por_done
|
~
pll
.
locked
|
rst
|
self
.
reset
),
]
...
...
litex_boards/targets/ulx3s.py
View file @
31e6997e
...
...
@@ -32,7 +32,7 @@ class _CRG(Module):
def
__init__
(
self
,
platform
,
sys_clk_freq
,
with_usb_pll
=
False
):
self
.
clock_domains
.
cd_sys
=
ClockDomain
()
self
.
clock_domains
.
cd_sys_ps
=
ClockDomain
(
reset_less
=
True
)
self
.
clock_domains
.
cd_sd
card
=
ClockDomain
()
self
.
clock_domains
.
cd_sd
=
ClockDomain
()
# # #
...
...
@@ -46,9 +46,9 @@ class _CRG(Module):
pll
.
register_clkin
(
clk25
,
25e6
)
pll
.
create_clkout
(
self
.
cd_sys
,
sys_clk_freq
)
pll
.
create_clkout
(
self
.
cd_sys_ps
,
sys_clk_freq
,
phase
=
90
)
pll
.
create_clkout
(
self
.
cd_sd
card
,
10e6
)
pll
.
create_clkout
(
self
.
cd_sd
,
10e6
)
self
.
specials
+=
AsyncResetSynchronizer
(
self
.
cd_sys
,
~
pll
.
locked
|
rst
)
self
.
specials
+=
AsyncResetSynchronizer
(
self
.
cd_sd
card
,
~
pll
.
locked
|
rst
)
self
.
specials
+=
AsyncResetSynchronizer
(
self
.
cd_sd
,
~
pll
.
locked
|
rst
)
# USB PLL
if
with_usb_pll
:
...
...
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