Commit 2cef54a9 authored by Florent Kermarrec's avatar Florent Kermarrec

targets/colorlight_5a_75x: avoid sys_clk_freq of 125MHz with etherbone (no longer required).

This allows creating SoCs with CPU, SDRAM and Etherbone enabled all together.
parent bfbee484
......@@ -103,9 +103,6 @@ class BaseSoC(SoCCore):
elif board == "5a-75e":
platform = colorlight_5a_75e.Platform(revision=revision)
if with_etherbone:
sys_clk_freq = int(125e6)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Colorlight " + board.upper(),
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