Commit 2ce24df7 authored by Florent Kermarrec's avatar Florent Kermarrec

platforms/genesys2: add internal_vref to 0.750v on bank 34 (DDR3).

parent 135c3871
...@@ -145,6 +145,7 @@ class Platform(XilinxPlatform): ...@@ -145,6 +145,7 @@ class Platform(XilinxPlatform):
def __init__(self): def __init__(self):
XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado") XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado")
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
def create_programmer(self): def create_programmer(self):
return OpenOCD("openocd_genesys2.cfg", "bscan_spi_xc7a325t.bit") return OpenOCD("openocd_genesys2.cfg", "bscan_spi_xc7a325t.bit")
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