From 2c9505eca699b923e9999d867155f00f7bdbee12 Mon Sep 17 00:00:00 2001
From: Raptor Engineering Development Team <support@raptorengineering.com>
Date: Wed, 21 Apr 2021 01:40:42 -0500
Subject: [PATCH] Enable IRQs on GPIO2

---
 litex_boards/targets/versa_ecp5.py | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/litex_boards/targets/versa_ecp5.py b/litex_boards/targets/versa_ecp5.py
index f9d4672..98e5cab 100755
--- a/litex_boards/targets/versa_ecp5.py
+++ b/litex_boards/targets/versa_ecp5.py
@@ -113,6 +113,7 @@ class BaseSoC(SoCCore):
     mem_map.update(SoCCore.mem_map)
 
     interrupt_map = {
+        "gpio2"         : 1,
         "ethmac"        : 2,
         "hostlpcslave"  : 3,
         "openfsimaster" : 4,
@@ -339,7 +340,8 @@ class BaseSoC(SoCCore):
         from litex.soc.cores.gpio import GPIOIn
 
         self.submodules.gpio2 = GPIOIn(
-            pads         = Cat(*[platform.request("user_dip_btn", i) for i in range(8)]))
+            pads         = Cat(*[platform.request("user_dip_btn", i) for i in range(8)]),
+            with_irq     = True)
         self.add_csr("gpio2")
 
         # Alphanumeric display -----------------------------------------------------------------------------
-- 
2.30.2