diff --git a/litex_boards/targets/versa_ecp5.py b/litex_boards/targets/versa_ecp5.py
index f9d4672afe099b5be03ba0f6db1c19aad1076a48..98e5cabac2c50d12260bb750d6a579560dc1a448 100755
--- a/litex_boards/targets/versa_ecp5.py
+++ b/litex_boards/targets/versa_ecp5.py
@@ -113,6 +113,7 @@ class BaseSoC(SoCCore):
     mem_map.update(SoCCore.mem_map)
 
     interrupt_map = {
+        "gpio2"         : 1,
         "ethmac"        : 2,
         "hostlpcslave"  : 3,
         "openfsimaster" : 4,
@@ -339,7 +340,8 @@ class BaseSoC(SoCCore):
         from litex.soc.cores.gpio import GPIOIn
 
         self.submodules.gpio2 = GPIOIn(
-            pads         = Cat(*[platform.request("user_dip_btn", i) for i in range(8)]))
+            pads         = Cat(*[platform.request("user_dip_btn", i) for i in range(8)]),
+            with_irq     = True)
         self.add_csr("gpio2")
 
         # Alphanumeric display -----------------------------------------------------------------------------