diff --git a/litex_boards/targets/ac701.py b/litex_boards/targets/ac701.py
index 12b3be14332fec69353c0a27f087ec416eaa00b6..93eb2764a27c3f0d68397e2871249891cb4a45e2 100755
--- a/litex_boards/targets/ac701.py
+++ b/litex_boards/targets/ac701.py
@@ -32,15 +32,16 @@ from liteeth.phy.s7rgmii import LiteEthPHYRGMII
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys       = ClockDomain()
         self.clock_domains.cd_sys4x     = ClockDomain(reset_less=True)
         self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
-        self.clock_domains.cd_clk200    = ClockDomain()
+        self.clock_domains.cd_idelay    = ClockDomain()
 
         # # #
 
         self.submodules.pll = pll = S7PLL(speedgrade=-1)
-        self.comb += pll.reset.eq(platform.request("cpu_reset"))
+        self.comb += pll.reset.eq(platform.request("cpu_reset") | self.rst)
         pll.register_clkin(platform.request("clk200"), 200e6)
         pll.create_clkout(self.cd_sys,       sys_clk_freq)
         pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
diff --git a/litex_boards/targets/acorn_cle_215.py b/litex_boards/targets/acorn_cle_215.py
index 2febf738ff5a9eedfa41f270ac72bf6b28de70e7..b2b774dd2f8367ba286a70ef9e08e51d0fa5da6a 100755
--- a/litex_boards/targets/acorn_cle_215.py
+++ b/litex_boards/targets/acorn_cle_215.py
@@ -52,6 +52,7 @@ from litepcie.software import generate_litepcie_software
 
 class CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys       = ClockDomain()
         self.clock_domains.cd_sys4x     = ClockDomain(reset_less=True)
         self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
@@ -62,6 +63,7 @@ class CRG(Module):
 
         # PLL
         self.submodules.pll = pll = S7PLL()
+        self.comb += pll.reset.eq(self.rst)
         pll.register_clkin(clk200, 200e6)
         pll.create_clkout(self.cd_sys,       sys_clk_freq)
         pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
diff --git a/litex_boards/targets/aller.py b/litex_boards/targets/aller.py
index 57be2c293c19b2558b512a8224227d097cecbccc..9d5fe069982da0be80e0f12fbad1a5058da86956 100755
--- a/litex_boards/targets/aller.py
+++ b/litex_boards/targets/aller.py
@@ -36,6 +36,7 @@ from litepcie.software import generate_litepcie_software
 
 class CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys       = ClockDomain()
         self.clock_domains.cd_sys4x     = ClockDomain(reset_less=True)
         self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
@@ -46,6 +47,7 @@ class CRG(Module):
 
         # PLL
         self.submodules.pll = pll = S7PLL()
+        self.comb += pll.reset.eq(self.rst)
         pll.register_clkin(clk100, 100e6)
         pll.create_clkout(self.cd_sys,       sys_clk_freq)
         pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
diff --git a/litex_boards/targets/alveo_u250.py b/litex_boards/targets/alveo_u250.py
index b6ca6e11e63a5d1c8f5b770c895149eb1ddca6d5..1cd0a2be41294a2b6bdf7f1bdb3a5ed73709ba33 100755
--- a/litex_boards/targets/alveo_u250.py
+++ b/litex_boards/targets/alveo_u250.py
@@ -33,6 +33,7 @@ from litepcie.software import generate_litepcie_software
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys    = ClockDomain()
         self.clock_domains.cd_sys4x  = ClockDomain(reset_less=True)
         self.clock_domains.cd_pll4x  = ClockDomain(reset_less=True)
@@ -41,7 +42,7 @@ class _CRG(Module):
         # # #
 
         self.submodules.pll = pll = USMMCM(speedgrade=-2)
-        self.comb += pll.reset.eq(0) # FIXME
+        self.comb += pll.reset.eq(self.rst)
         pll.register_clkin(platform.request("clk300", 0), 300e6)
         pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
         pll.create_clkout(self.cd_idelay, 500e6, with_reset=False)
diff --git a/litex_boards/targets/arty.py b/litex_boards/targets/arty.py
index e5a0727e158f045015a3f877f3fbad78263e3eaa..f82f7295c696b3f51670a437d4357814ca7489e9 100755
--- a/litex_boards/targets/arty.py
+++ b/litex_boards/targets/arty.py
@@ -29,6 +29,7 @@ from liteeth.phy.mii import LiteEthPHYMII
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys       = ClockDomain()
         self.clock_domains.cd_sys4x     = ClockDomain(reset_less=True)
         self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
@@ -38,7 +39,7 @@ class _CRG(Module):
         # # #
 
         self.submodules.pll = pll = S7PLL(speedgrade=-1)
-        self.comb += pll.reset.eq(~platform.request("cpu_reset"))
+        self.comb += pll.reset.eq(~platform.request("cpu_reset") | self.rst)
         pll.register_clkin(platform.request("clk100"), 100e6)
         pll.create_clkout(self.cd_sys,       sys_clk_freq)
         pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
diff --git a/litex_boards/targets/arty_s7.py b/litex_boards/targets/arty_s7.py
index 192b63d1b23964c9d1341d840a8112a552798b51..9075474c85fc20458ff3c33e0119213247eea4d8 100755
--- a/litex_boards/targets/arty_s7.py
+++ b/litex_boards/targets/arty_s7.py
@@ -28,6 +28,7 @@ from litedram.phy import s7ddrphy
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys       = ClockDomain()
         self.clock_domains.cd_sys2x     = ClockDomain(reset_less=True)
         self.clock_domains.cd_sys4x     = ClockDomain(reset_less=True)
@@ -37,7 +38,7 @@ class _CRG(Module):
         # # #
 
         self.submodules.pll = pll = S7PLL(speedgrade=-1)
-        self.comb += pll.reset.eq(~platform.request("cpu_reset"))
+        self.comb += pll.reset.eq(~platform.request("cpu_reset") | self.rst)
         pll.register_clkin(platform.request("clk100"), 100e6)
         pll.create_clkout(self.cd_sys,       sys_clk_freq)
         pll.create_clkout(self.cd_sys2x,     2*sys_clk_freq)
@@ -67,8 +68,7 @@ class BaseSoC(SoCCore):
             self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
                 memtype        = "DDR3",
                 nphases        = 4,
-                sys_clk_freq   = sys_clk_freq,
-                interface_type = "MEMORY")
+                sys_clk_freq   = sys_clk_freq)
             self.add_csr("ddrphy")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,
diff --git a/litex_boards/targets/c10lprefkit.py b/litex_boards/targets/c10lprefkit.py
index 2b46024e69c7970538fb2157500e5461a451d4a9..1d6b15260f7e85496ca80ba15a62f6e276578927 100755
--- a/litex_boards/targets/c10lprefkit.py
+++ b/litex_boards/targets/c10lprefkit.py
@@ -32,6 +32,7 @@ from litehyperbus.core.hyperbus import HyperRAM
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys    = ClockDomain()
         self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
 
@@ -42,7 +43,7 @@ class _CRG(Module):
 
         # PLL
         self.submodules.pll = pll = Cyclone10LPPLL(speedgrade="-A7")
-        self.comb += pll.reset.eq(~platform.request("cpu_reset"))
+        self.comb += pll.reset.eq(~platform.request("cpu_reset") | self.rst)
         pll.register_clkin(clk12, 12e6)
         pll.create_clkout(self.cd_sys,    sys_clk_freq)
         pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
diff --git a/litex_boards/targets/camlink_4k.py b/litex_boards/targets/camlink_4k.py
index e0eadd398753d3a170710deb8d86fc5af26a65d1..4f12909eeed5598a5a0488fb8f9160d3ebf28cbc 100755
--- a/litex_boards/targets/camlink_4k.py
+++ b/litex_boards/targets/camlink_4k.py
@@ -29,6 +29,7 @@ from litedram.phy import ECP5DDRPHY
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_init    = ClockDomain()
         self.clock_domains.cd_por     = ClockDomain(reset_less=True)
         self.clock_domains.cd_sys     = ClockDomain()
@@ -51,7 +52,7 @@ class _CRG(Module):
 
         # pll
         self.submodules.pll = pll = ECP5PLL()
-        self.comb += pll.reset.eq(~por_done)
+        self.comb += pll.reset.eq(~por_done | self.rst)
         pll.register_clkin(clk27, 27e6)
         pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
         pll.create_clkout(self.cd_init, 27e6)
diff --git a/litex_boards/targets/colorlight_5a_75x.py b/litex_boards/targets/colorlight_5a_75x.py
index c83d6669c0c36afb34688552bb0b64a7e3c7aab1..e9a1563a0e0d926dd2d6de4e8a77042f792e9df1 100755
--- a/litex_boards/targets/colorlight_5a_75x.py
+++ b/litex_boards/targets/colorlight_5a_75x.py
@@ -66,6 +66,7 @@ from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq, use_internal_osc=False, with_usb_pll=False, with_rst=True, sdram_rate="1:1"):
+        self.rst = Signal()
         self.clock_domains.cd_sys    = ClockDomain()
         if sdram_rate == "1:2":
             self.clock_domains.cd_sys2x    = ClockDomain()
@@ -91,7 +92,7 @@ class _CRG(Module):
 
         # PLL
         self.submodules.pll = pll = ECP5PLL()
-        self.comb += pll.reset.eq(~rst_n)
+        self.comb += pll.reset.eq(~rst_n | self.rst)
         pll.register_clkin(clk, clk_freq)
         pll.create_clkout(self.cd_sys,    sys_clk_freq)
         if sdram_rate == "1:2":
@@ -103,7 +104,7 @@ class _CRG(Module):
         # USB PLL
         if with_usb_pll:
             self.submodules.usb_pll = usb_pll = ECP5PLL()
-            self.comb += usb_pll.reset.eq(~rst_n)
+            self.comb += usb_pll.reset.eq(~rst_n | self.rst)
             usb_pll.register_clkin(clk, clk_freq)
             self.clock_domains.cd_usb_12 = ClockDomain()
             self.clock_domains.cd_usb_48 = ClockDomain()
diff --git a/litex_boards/targets/crosslink_nx_evn.py b/litex_boards/targets/crosslink_nx_evn.py
index f01911ca06b6c9a7cee37ea3e2ae025d45bf1ab8..dcb4a0357fb626cdebd6c2ee32f546ee12a3b8b3 100755
--- a/litex_boards/targets/crosslink_nx_evn.py
+++ b/litex_boards/targets/crosslink_nx_evn.py
@@ -33,6 +33,7 @@ mB = 1024*kB
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys = ClockDomain()
         self.clock_domains.cd_por = ClockDomain()
 
@@ -49,7 +50,7 @@ class _CRG(Module):
         self.comb += self.cd_por.clk.eq(self.cd_sys.clk)
         self.sync.por += If(por_counter != 0, por_counter.eq(por_counter - 1))
         self.specials += AsyncResetSynchronizer(self.cd_por, ~rst_n)
-        self.specials += AsyncResetSynchronizer(self.cd_sys, (por_counter != 0))
+        self.specials += AsyncResetSynchronizer(self.cd_sys, (por_counter != 0) | self.rst)
 
 
 # BaseSoC ------------------------------------------------------------------------------------------
diff --git a/litex_boards/targets/crosslink_nx_vip.py b/litex_boards/targets/crosslink_nx_vip.py
index 299f000a0eb759ba2c55e6b4e87832d752a8dee0..1da6c5bbd78b69ee342f8aef571014e1123cc43e 100755
--- a/litex_boards/targets/crosslink_nx_vip.py
+++ b/litex_boards/targets/crosslink_nx_vip.py
@@ -39,6 +39,7 @@ mB = 1024*kB
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys = ClockDomain()
         self.clock_domains.cd_por = ClockDomain()
 
@@ -55,7 +56,7 @@ class _CRG(Module):
         self.comb += self.cd_por.clk.eq(self.cd_sys.clk)
         self.sync.por += If(por_counter != 0, por_counter.eq(por_counter - 1))
         self.specials += AsyncResetSynchronizer(self.cd_por, ~rst_n)
-        self.specials += AsyncResetSynchronizer(self.cd_sys, (por_counter != 0))
+        self.specials += AsyncResetSynchronizer(self.cd_sys, (por_counter != 0) | self.rst)
 
 
 # BaseSoC ------------------------------------------------------------------------------------------
diff --git a/litex_boards/targets/de0nano.py b/litex_boards/targets/de0nano.py
index c8717bef676e186c10f86c4f3927b2dd8f354e89..8f3d5b817e7aafeaeb75ae70cf5f5558aab543a4 100755
--- a/litex_boards/targets/de0nano.py
+++ b/litex_boards/targets/de0nano.py
@@ -29,6 +29,7 @@ from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq, sdram_rate="1:1"):
+        self.rst = Signal()
         self.clock_domains.cd_sys    = ClockDomain()
         if sdram_rate == "1:2":
             self.clock_domains.cd_sys2x    = ClockDomain()
@@ -43,6 +44,7 @@ class _CRG(Module):
 
         # PLL
         self.submodules.pll = pll = CycloneIVPLL(speedgrade="-6")
+        self.comb += pll.reset.eq(self.rst)
         pll.register_clkin(clk50, 50e6)
         pll.create_clkout(self.cd_sys,    sys_clk_freq)
         if sdram_rate == "1:2":
diff --git a/litex_boards/targets/de10lite.py b/litex_boards/targets/de10lite.py
index 8374a3e0377b05aab025273e1b9e0116fc20c7ef..10ff746de6fddd01b2a19e87fa726823562532f0 100755
--- a/litex_boards/targets/de10lite.py
+++ b/litex_boards/targets/de10lite.py
@@ -32,6 +32,7 @@ from litevideo.terminal.core import Terminal
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys    = ClockDomain()
         self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
         self.clock_domains.cd_vga    = ClockDomain(reset_less=True)
@@ -43,6 +44,7 @@ class _CRG(Module):
 
         # PLL
         self.submodules.pll = pll = Max10PLL(speedgrade="-7")
+        self.comb += pll.reset.eq(self.rst)
         pll.register_clkin(clk50, 50e6)
         pll.create_clkout(self.cd_sys,    sys_clk_freq)
         pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
diff --git a/litex_boards/targets/de10nano.py b/litex_boards/targets/de10nano.py
index af0897b5189dffa0de4f522f8ed146313171afa2..2dbd7573cbdf0b2c0e8cb39f069ec9759ddb2cf4 100755
--- a/litex_boards/targets/de10nano.py
+++ b/litex_boards/targets/de10nano.py
@@ -32,6 +32,7 @@ from litevideo.terminal.core import Terminal
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq, with_sdram=False, sdram_rate="1:1"):
+        self.rst = Signal()
         self.clock_domains.cd_sys    = ClockDomain()
         if sdram_rate == "1:2":
             self.clock_domains.cd_sys2x    = ClockDomain()
@@ -47,6 +48,7 @@ class _CRG(Module):
 
         # PLL
         self.submodules.pll = pll = CycloneVPLL(speedgrade="-I7")
+        self.comb += pll.reset.eq(self.rst)
         pll.register_clkin(clk50, 50e6)
         pll.create_clkout(self.cd_sys,    sys_clk_freq)
         if sdram_rate == "1:2":
diff --git a/litex_boards/targets/de1soc.py b/litex_boards/targets/de1soc.py
index a9da9bf651f7a401cdf890012aa61fc593083161..574d82c034c0771da4302a92ef729e24cd1b13cd 100755
--- a/litex_boards/targets/de1soc.py
+++ b/litex_boards/targets/de1soc.py
@@ -28,6 +28,7 @@ from litedram.phy import GENSDRPHY
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys    = ClockDomain()
         self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
 
@@ -38,6 +39,7 @@ class _CRG(Module):
 
         # PLL
         self.submodules.pll = pll = CycloneVPLL(speedgrade="-C6")
+        self.comb += pll.reset.eq(self.rst)
         pll.register_clkin(clk50, 50e6)
         pll.create_clkout(self.cd_sys,    sys_clk_freq)
         pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
diff --git a/litex_boards/targets/de2_115.py b/litex_boards/targets/de2_115.py
index 12edf064c8df4d5efe84023e80eca18c7f3b159e..e108ed0792fe675167c2db3274e56dca7c15229d 100755
--- a/litex_boards/targets/de2_115.py
+++ b/litex_boards/targets/de2_115.py
@@ -28,6 +28,7 @@ from litedram.phy import GENSDRPHY
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys    = ClockDomain()
         self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
 
@@ -38,6 +39,7 @@ class _CRG(Module):
 
         # PLL
         self.submodules.pll = pll = CycloneIVPLL(speedgrade="-7")
+        self.comb += pll.reset.eq(self.rst)
         pll.register_clkin(clk50, 50e6)
         pll.create_clkout(self.cd_sys,    sys_clk_freq)
         pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
diff --git a/litex_boards/targets/ecp5_evn.py b/litex_boards/targets/ecp5_evn.py
index 49688e00611c089837057b3392c5b845a44d8859..f97e600961d547f49535a7b1269329305be4905a 100755
--- a/litex_boards/targets/ecp5_evn.py
+++ b/litex_boards/targets/ecp5_evn.py
@@ -23,6 +23,7 @@ from litex.soc.cores.led import LedChaser
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq, x5_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys = ClockDomain()
 
         # # #
@@ -37,7 +38,7 @@ class _CRG(Module):
 
         # pll
         self.submodules.pll = pll = ECP5PLL()
-        self.comb += pll.reset.eq(~rst_n)
+        self.comb += pll.reset.eq(~rst_n | self.rst)
         pll.register_clkin(clk, x5_clk_freq or 12e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)
 
diff --git a/litex_boards/targets/ecpix5.py b/litex_boards/targets/ecpix5.py
index cfe72b678d003ec31495570cc6cfb2eeb23fe7a2..0a21bcb179c553c3355cde5652681d56ff303c74 100755
--- a/litex_boards/targets/ecpix5.py
+++ b/litex_boards/targets/ecpix5.py
@@ -30,6 +30,7 @@ from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_init    = ClockDomain()
         self.clock_domains.cd_por     = ClockDomain(reset_less=True)
         self.clock_domains.cd_sys     = ClockDomain()
@@ -54,7 +55,7 @@ class _CRG(Module):
 
         # PLL
         self.submodules.pll = pll = ECP5PLL()
-        self.comb += pll.reset.eq(~por_done | ~rst_n)
+        self.comb += pll.reset.eq(~por_done | ~rst_n | self.rst)
         pll.register_clkin(clk100, 100e6)
         pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
         pll.create_clkout(self.cd_init, 25e6)
@@ -69,8 +70,8 @@ class _CRG(Module):
                 i_CLKI    = self.cd_sys2x.clk,
                 i_RST     = self.reset,
                 o_CDIVX   = self.cd_sys.clk),
-            AsyncResetSynchronizer(self.cd_sys,   ~pll.locked | self.reset),
-            AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset),
+            AsyncResetSynchronizer(self.cd_sys,   ~pll.locked | self.reset | self.rst),
+            AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset | self.rst),
         ]
 
 # BaseSoC ------------------------------------------------------------------------------------------
diff --git a/litex_boards/targets/fk33.py b/litex_boards/targets/fk33.py
index 310b7bb2e07b0fc2cd5de8dc05c2c6c1a18e0321..c112695be856ef7b3c57968db40cdca58aa86924 100755
--- a/litex_boards/targets/fk33.py
+++ b/litex_boards/targets/fk33.py
@@ -29,11 +29,13 @@ from litepcie.software import generate_litepcie_software
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys    = ClockDomain()
 
         # # #
 
         self.submodules.pll = pll = USPMMCM(speedgrade=-2)
+        self.comb += pll.reset.eq(self.rst)
         pll.register_clkin(platform.request("clk200"), 200e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)
 
diff --git a/litex_boards/targets/fomu.py b/litex_boards/targets/fomu.py
index f8a73fd977fdd732ff14eb31ffbc38259d7ea181..7ebce416ff1463ed2e1bd286cf798f0197e9c2ee 100755
--- a/litex_boards/targets/fomu.py
+++ b/litex_boards/targets/fomu.py
@@ -33,6 +33,7 @@ mB = 1024*kB
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
         assert sys_clk_freq == 12e6
+        self.rst = Signal()
         self.clock_domains.cd_sys    = ClockDomain()
         self.clock_domains.cd_por    = ClockDomain(reset_less=True)
         self.clock_domains.cd_usb_12 = ClockDomain()
@@ -53,6 +54,7 @@ class _CRG(Module):
 
         # USB PLL
         self.submodules.pll = pll = iCE40PLL()
+        self.comb += pll.reset.eq(self.rst)
         pll.clko_freq_range = ( 12e6,  275e9) # FIXME: improve iCE40PLL to avoid lowering clko_freq_min.
         pll.register_clkin(clk48, 48e6)
         pll.create_clkout(self.cd_usb_12, 12e6, with_reset=False)
diff --git a/litex_boards/targets/genesys2.py b/litex_boards/targets/genesys2.py
index b2ea77d9337416353c43d01b521340980ee6e527..002db8bfe950c647a98cb2acfabb1d1601cca774 100755
--- a/litex_boards/targets/genesys2.py
+++ b/litex_boards/targets/genesys2.py
@@ -28,6 +28,7 @@ from liteeth.phy.s7rgmii import LiteEthPHYRGMII
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys    = ClockDomain()
         self.clock_domains.cd_sys4x  = ClockDomain(reset_less=True)
         self.clock_domains.cd_idelay = ClockDomain()
@@ -35,7 +36,7 @@ class _CRG(Module):
         # # #
 
         self.submodules.pll = pll = S7MMCM(speedgrade=-2)
-        self.comb += pll.reset.eq(~platform.request("cpu_reset_n"))
+        self.comb += pll.reset.eq(~platform.request("cpu_reset_n") | self.rst)
         pll.register_clkin(platform.request("clk200"), 200e6)
         pll.create_clkout(self.cd_sys,    sys_clk_freq)
         pll.create_clkout(self.cd_sys4x,  4*sys_clk_freq)
diff --git a/litex_boards/targets/hadbadge.py b/litex_boards/targets/hadbadge.py
index 9a6e8fe68be4a38478caf761288a997853a4a7f6..c35ce9d742debfeffc32058101577a82a5546443 100755
--- a/litex_boards/targets/hadbadge.py
+++ b/litex_boards/targets/hadbadge.py
@@ -35,6 +35,7 @@ from litedram.modules import AS4C32M8
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys    = ClockDomain()
         self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
 
@@ -45,6 +46,7 @@ class _CRG(Module):
 
         # PLL
         self.submodules.pll = pll = ECP5PLL()
+        self.comb += pll.reset.eq(self.rst)
         pll.register_clkin(clk8, 8e6)
         pll.create_clkout(self.cd_sys,    sys_clk_freq)
         pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
diff --git a/litex_boards/targets/icebreaker.py b/litex_boards/targets/icebreaker.py
index 3440d37d624639dc4ff5d69bdb78914b7cda3fc4..806f27afd016678367e75841ffa8fe012b0bf71a 100755
--- a/litex_boards/targets/icebreaker.py
+++ b/litex_boards/targets/icebreaker.py
@@ -40,6 +40,7 @@ mB = 1024*kB
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys = ClockDomain()
         self.clock_domains.cd_por = ClockDomain(reset_less=True)
 
@@ -58,7 +59,7 @@ class _CRG(Module):
 
         # PLL
         self.submodules.pll = pll = iCE40PLL(primitive="SB_PLL40_PAD")
-        self.comb += pll.reset.eq(~rst_n)
+        self.comb += pll.reset.eq(~rst_n | self.rst)
         pll.register_clkin(clk12, 12e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=False)
         self.specials += AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked)
diff --git a/litex_boards/targets/kc705.py b/litex_boards/targets/kc705.py
index 4c678806df8eb28e3832e472fc4b55292c5863bf..ad5a21cb92c14bcc7b0523c485cc91a7f23c79b1 100755
--- a/litex_boards/targets/kc705.py
+++ b/litex_boards/targets/kc705.py
@@ -30,6 +30,7 @@ from liteeth.phy import LiteEthPHY
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys    = ClockDomain()
         self.clock_domains.cd_sys4x  = ClockDomain(reset_less=True)
         self.clock_domains.cd_idelay = ClockDomain()
@@ -37,7 +38,7 @@ class _CRG(Module):
         # # #
 
         self.submodules.pll = pll = S7MMCM(speedgrade=-2)
-        self.comb += pll.reset.eq(platform.request("cpu_reset"))
+        self.comb += pll.reset.eq(platform.request("cpu_reset") | self.rst)
         pll.register_clkin(platform.request("clk200"), 200e6)
         pll.create_clkout(self.cd_sys,    sys_clk_freq)
         pll.create_clkout(self.cd_sys4x,  4*sys_clk_freq)
diff --git a/litex_boards/targets/kcu105.py b/litex_boards/targets/kcu105.py
index 65fb8ed3f508db8398c201b6ce8bb40d49c5186a..9668934a936e2a74816c6dc98bd00986b716448e 100755
--- a/litex_boards/targets/kcu105.py
+++ b/litex_boards/targets/kcu105.py
@@ -28,6 +28,7 @@ from liteeth.phy.ku_1000basex import KU_1000BASEX
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys    = ClockDomain()
         self.clock_domains.cd_sys4x  = ClockDomain(reset_less=True)
         self.clock_domains.cd_pll4x  = ClockDomain(reset_less=True)
@@ -37,7 +38,7 @@ class _CRG(Module):
         # # #
 
         self.submodules.pll = pll = USMMCM(speedgrade=-2)
-        self.comb += pll.reset.eq(platform.request("cpu_reset"))
+        self.comb += pll.reset.eq(platform.request("cpu_reset") | self.rst)
         pll.register_clkin(platform.request("clk125"), 125e6)
         pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
         pll.create_clkout(self.cd_idelay, 200e6, with_reset=False)
diff --git a/litex_boards/targets/kx2.py b/litex_boards/targets/kx2.py
index ae31996585daab6785a3dbb6bd46506d05e688d7..e581ad0b000d9860efa3e8f02ec4116e6deee06d 100755
--- a/litex_boards/targets/kx2.py
+++ b/litex_boards/targets/kx2.py
@@ -26,6 +26,7 @@ from litedram.phy import s7ddrphy
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys    = ClockDomain()
         self.clock_domains.cd_sys4x  = ClockDomain(reset_less=True)
         self.clock_domains.cd_idelay = ClockDomain()
@@ -33,7 +34,7 @@ class _CRG(Module):
         # # #
 
         self.submodules.pll = pll = S7MMCM(speedgrade=-2)
-        self.comb += pll.reset.eq(~platform.request("cpu_reset_n"))
+        self.comb += pll.reset.eq(~platform.request("cpu_reset_n") | self.rst)
         pll.register_clkin(platform.request("clk200"), 200e6)
         pll.create_clkout(self.cd_sys,    sys_clk_freq)
         pll.create_clkout(self.cd_sys4x,  4*sys_clk_freq)
diff --git a/litex_boards/targets/linsn_rv901t.py b/litex_boards/targets/linsn_rv901t.py
index d810edd15147ea300d72bebb3409296542230cfe..c57951fc17591b061e86b90f0e0d8a5d5c8405bc 100755
--- a/litex_boards/targets/linsn_rv901t.py
+++ b/litex_boards/targets/linsn_rv901t.py
@@ -31,6 +31,7 @@ from liteeth.mac import LiteEthMAC
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys    = ClockDomain()
         self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
 
@@ -39,6 +40,7 @@ class _CRG(Module):
         clk25 = platform.request("clk25")
 
         self.submodules.pll = pll = S6PLL(speedgrade=-2)
+        self.comb += pll.reset.eq(self.rst)
         pll.register_clkin(clk25, 25e6)
         pll.create_clkout(self.cd_sys,    sys_clk_freq)
         pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
diff --git a/litex_boards/targets/logicbone.py b/litex_boards/targets/logicbone.py
index beff7fde78f31de5734663b78e4c8cbf6293cefd..b35624df5256a72b811972702e701ceccfb28a39 100755
--- a/litex_boards/targets/logicbone.py
+++ b/litex_boards/targets/logicbone.py
@@ -31,6 +31,7 @@ from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq, with_usb_pll=False):
+        self.rst = Signal()
         self.clock_domains.cd_init     = ClockDomain()
         self.clock_domains.cd_por      = ClockDomain(reset_less=True)
         self.clock_domains.cd_sys      = ClockDomain()
@@ -55,7 +56,7 @@ class _CRG(Module):
         # PLL
         sys2x_clk_ecsout = Signal()
         self.submodules.pll = pll = ECP5PLL()
-        self.comb += pll.reset.eq(~por_done)
+        self.comb += pll.reset.eq(~por_done | self.rst)
         pll.register_clkin(clk25, 25e6)
         pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
         pll.create_clkout(self.cd_init, 24e6)
@@ -84,7 +85,7 @@ class _CRG(Module):
             self.clock_domains.cd_usb_48 = ClockDomain()
             usb_pll = ECP5PLL()
             self.submodules += usb_pll
-            self.comb += usb_pll.reset.eq(~por_done)
+            self.comb += usb_pll.reset.eq(~por_done | self.rst)
             usb_pll.register_clkin(clk25, 25e6)
             usb_pll.create_clkout(self.cd_usb_48, 48e6)
             usb_pll.create_clkout(self.cd_usb_12, 12e6)
diff --git a/litex_boards/targets/mercury_xu5.py b/litex_boards/targets/mercury_xu5.py
index 89803e2ba5d51b90c177acd1a8a00c73b891fb9f..8a774947448d61a24ffb2c61faa99a6d139c7d91 100755
--- a/litex_boards/targets/mercury_xu5.py
+++ b/litex_boards/targets/mercury_xu5.py
@@ -27,6 +27,7 @@ from litedram.phy import usddrphy
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys    = ClockDomain()
         self.clock_domains.cd_sys4x  = ClockDomain(reset_less=True)
         self.clock_domains.cd_pll4x  = ClockDomain(reset_less=True)
@@ -35,6 +36,7 @@ class _CRG(Module):
         # # #
 
         self.submodules.pll = pll = USMMCM(speedgrade=-1)
+        self.comb += pll.reset.eq(self.rst)
         pll.register_clkin(platform.request("clk100"), 100e6)
 
         pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
diff --git a/litex_boards/targets/mimas_a7.py b/litex_boards/targets/mimas_a7.py
index 26af0d1d930f80908df8c8056961b25a436ec7ce..d7c7ea861f1277a2f13b07ae3c6bd7b6b9b1f4f4 100755
--- a/litex_boards/targets/mimas_a7.py
+++ b/litex_boards/targets/mimas_a7.py
@@ -30,6 +30,7 @@ from liteeth.phy.s7rgmii import LiteEthPHYRGMII
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys       = ClockDomain()
         self.clock_domains.cd_sys4x     = ClockDomain(reset_less=True)
         self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
@@ -38,7 +39,7 @@ class _CRG(Module):
         # # #
 
         self.submodules.pll = pll = S7PLL(speedgrade=-1)
-        self.comb += pll.reset.eq(platform.request("cpu_reset"))
+        self.comb += pll.reset.eq(platform.request("cpu_reset") | self.rst)
         pll.register_clkin(platform.request("clk100"), 100e6)
         pll.create_clkout(self.cd_sys,       sys_clk_freq)
         pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
diff --git a/litex_boards/targets/minispartan6.py b/litex_boards/targets/minispartan6.py
index 15fd3b014d09222388075cd551fb03963d7890df..69372c661fc60226cd4e04fa242cee6ca93b02de 100755
--- a/litex_boards/targets/minispartan6.py
+++ b/litex_boards/targets/minispartan6.py
@@ -32,6 +32,7 @@ from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq, sdram_rate="1:1"):
+        self.rst = Signal()
         self.clock_domains.cd_sys    = ClockDomain()
         if sdram_rate == "1:2":
             self.clock_domains.cd_sys2x    = ClockDomain()
@@ -46,6 +47,7 @@ class _CRG(Module):
 
         # PLL
         self.submodules.pll = pll = S6PLL(speedgrade=-1)
+        self.comb += pll.reset.eq(self.rst)
         pll.register_clkin(clk32, 32e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)
         if sdram_rate == "1:2":
diff --git a/litex_boards/targets/mist.py b/litex_boards/targets/mist.py
index 9307442892c7f49cb13717c012c8012481967c77..ae1a8d222c481db04387383421f698f1a9c0e551 100755
--- a/litex_boards/targets/mist.py
+++ b/litex_boards/targets/mist.py
@@ -32,6 +32,7 @@ from litevideo.terminal.core import Terminal
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys    = ClockDomain()
         self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
         self.clock_domains.cd_vga    = ClockDomain(reset_less=True)
@@ -43,6 +44,7 @@ class _CRG(Module):
 
         # PLL
         self.submodules.pll = pll = CycloneIVPLL(speedgrade="-8")
+        self.comb += pll.reset.eq(self.rst)
         pll.register_clkin(clk27, 27e6)
         pll.create_clkout(self.cd_sys,    sys_clk_freq)
         pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
diff --git a/litex_boards/targets/nereid.py b/litex_boards/targets/nereid.py
index 1a72402cabe019c6752bd9dd1c1b9fe643b9597a..366ad6c4023016d8080de5542339b68f21840ea0 100755
--- a/litex_boards/targets/nereid.py
+++ b/litex_boards/targets/nereid.py
@@ -35,6 +35,7 @@ from litepcie.software import generate_litepcie_software
 
 class CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys    = ClockDomain()
         self.clock_domains.cd_sys4x  = ClockDomain(reset_less=True)
         self.clock_domains.cd_idelay = ClockDomain()
@@ -44,6 +45,7 @@ class CRG(Module):
 
         # PLL
         self.submodules.pll = pll = S7PLL()
+        self.comb += pll.reset.eq(self.rst)
         pll.register_clkin(clk100, 100e6)
         pll.create_clkout(self.cd_sys,    sys_clk_freq)
         pll.create_clkout(self.cd_sys4x,  4*sys_clk_freq)
diff --git a/litex_boards/targets/netv2.py b/litex_boards/targets/netv2.py
index 964130daa45fa3d72c359ef0ba38d6299a266be3..0196fb28a3412ef30294ae3fef4faa90edfacac3 100755
--- a/litex_boards/targets/netv2.py
+++ b/litex_boards/targets/netv2.py
@@ -28,6 +28,7 @@ from liteeth.phy.rmii import LiteEthPHYRMII
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys       = ClockDomain()
         self.clock_domains.cd_sys4x     = ClockDomain(reset_less=True)
         self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
@@ -38,6 +39,7 @@ class _CRG(Module):
         # # #
 
         self.submodules.pll = pll = S7PLL(speedgrade=-1)
+        self.comb += pll.reset.eq(self.rst)
         pll.register_clkin(platform.request("clk50"), 50e6)
         pll.create_clkout(self.cd_sys,       sys_clk_freq)
         pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
diff --git a/litex_boards/targets/nexys4ddr.py b/litex_boards/targets/nexys4ddr.py
index fca79a661011eeaea81024257d5efa8250bc22e6..d72b76682c6bf8b5bba605c3c8568d0be28dbdac 100755
--- a/litex_boards/targets/nexys4ddr.py
+++ b/litex_boards/targets/nexys4ddr.py
@@ -28,6 +28,7 @@ from liteeth.phy.rmii import LiteEthPHYRMII
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys       = ClockDomain()
         self.clock_domains.cd_sys2x     = ClockDomain(reset_less=True)
         self.clock_domains.cd_sys2x_dqs = ClockDomain(reset_less=True)
@@ -37,7 +38,7 @@ class _CRG(Module):
         # # #
 
         self.submodules.pll = pll = S7MMCM(speedgrade=-1)
-        self.comb += pll.reset.eq(~platform.request("cpu_reset"))
+        self.comb += pll.reset.eq(~platform.request("cpu_reset") | self.rst)
         pll.register_clkin(platform.request("clk100"), 100e6)
         pll.create_clkout(self.cd_sys,       sys_clk_freq)
         pll.create_clkout(self.cd_sys2x,     2*sys_clk_freq)
diff --git a/litex_boards/targets/nexys_video.py b/litex_boards/targets/nexys_video.py
index 96c35c3c0735dcdb0b631356cf7327db52df1633..17b7bb7cbfd473d33249a59a94786b011dd51edd 100755
--- a/litex_boards/targets/nexys_video.py
+++ b/litex_boards/targets/nexys_video.py
@@ -28,6 +28,7 @@ from liteeth.phy.s7rgmii import LiteEthPHYRGMII
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys       = ClockDomain()
         self.clock_domains.cd_sys4x     = ClockDomain(reset_less=True)
         self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
@@ -37,7 +38,7 @@ class _CRG(Module):
         # # #
 
         self.submodules.pll = pll = S7MMCM(speedgrade=-1)
-        self.comb += pll.reset.eq(~platform.request("cpu_reset"))
+        self.comb += pll.reset.eq(~platform.request("cpu_reset") | self.rst)
         pll.register_clkin(platform.request("clk100"), 100e6)
         pll.create_clkout(self.cd_sys,       sys_clk_freq)
         pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py
index 646055f2c652d0b3d80f51fb6f2c655d6d06eb3c..5bbe14abe5f94b4acdd9e82251005b403b3a87d5 100755
--- a/litex_boards/targets/orangecrab.py
+++ b/litex_boards/targets/orangecrab.py
@@ -31,6 +31,7 @@ from litedram.phy import ECP5DDRPHY
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq, with_usb_pll=False):
+        self.rst = Signal()
         self.clock_domains.cd_por     = ClockDomain(reset_less=True)
         self.clock_domains.cd_sys     = ClockDomain()
 
@@ -49,7 +50,7 @@ class _CRG(Module):
 
         # PLL
         self.submodules.pll = pll = ECP5PLL()
-        self.comb += pll.reset.eq(~por_done | ~rst_n)
+        self.comb += pll.reset.eq(~por_done | ~rst_n | self.rst)
         pll.register_clkin(clk48, 48e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)
 
@@ -59,7 +60,7 @@ class _CRG(Module):
             self.clock_domains.cd_usb_48 = ClockDomain()
             usb_pll = ECP5PLL()
             self.submodules += usb_pll
-            self.comb += usb_pll.reset.eq(~por_done | ~rst_n)
+            self.comb += usb_pll.reset.eq(~por_done | ~rst_n | self.rst)
             usb_pll.register_clkin(clk48, 48e6)
             usb_pll.create_clkout(self.cd_usb_48, 48e6)
             usb_pll.create_clkout(self.cd_usb_12, 12e6)
diff --git a/litex_boards/targets/pano_logic_g2.py b/litex_boards/targets/pano_logic_g2.py
index 91a5b4551a6d250bfdf2e5d767e0530d54ad5093..0d4d42631bbe72c81fa49c0487b3e2f9a5f5917c 100755
--- a/litex_boards/targets/pano_logic_g2.py
+++ b/litex_boards/targets/pano_logic_g2.py
@@ -25,6 +25,7 @@ from liteeth.phy import LiteEthPHY
 
 class _CRG(Module):
     def __init__(self, platform, clk_freq, with_ethernet=False):
+        self.rst = Signal()
         self.clock_domains.cd_sys    = ClockDomain()
 
         # # #
@@ -35,7 +36,7 @@ class _CRG(Module):
             self.comb += platform.request("eth_rst_n").eq(1)
 
         self.submodules.pll = pll = S6PLL(speedgrade=-2)
-        self.comb += pll.reset.eq(~platform.request("user_btn_n"))
+        self.comb += pll.reset.eq(~platform.request("user_btn_n") | self.rst)
         pll.register_clkin(platform.request("clk125"), 125e6)
         pll.create_clkout(self.cd_sys, clk_freq)
 
diff --git a/litex_boards/targets/pipistrello.py b/litex_boards/targets/pipistrello.py
index 80d48fa5fb8393d5a7381e98974046b273d9fac0..4cae76cf271d794f794adae0bce76fcb397c5c17 100755
--- a/litex_boards/targets/pipistrello.py
+++ b/litex_boards/targets/pipistrello.py
@@ -32,6 +32,7 @@ from litedram.phy import s6ddrphy
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys           = ClockDomain()
         self.clock_domains.cd_sdram_half    = ClockDomain()
         self.clock_domains.cd_sdram_full_wr = ClockDomain()
@@ -104,7 +105,7 @@ class _CRG(Module):
         )
 
         # Power on reset
-        reset = platform.request("user_btn") | self.reset
+        reset = platform.request("user_btn") | self.reset | self.rst
         self.clock_domains.cd_por = ClockDomain()
         por = Signal(max=1 << 11, reset=(1 << 11) - 1)
         self.sync.por += If(por != 0, por.eq(por - 1))
diff --git a/litex_boards/targets/tagus.py b/litex_boards/targets/tagus.py
index 3212c756a7438f9c576952e9eb018a27217a7db4..96903e41369a1c6649f71066b108266be6ad4e76 100755
--- a/litex_boards/targets/tagus.py
+++ b/litex_boards/targets/tagus.py
@@ -36,6 +36,7 @@ from litepcie.software import generate_litepcie_software
 
 class CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys       = ClockDomain()
         self.clock_domains.cd_sys4x     = ClockDomain(reset_less=True)
         self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
@@ -46,6 +47,7 @@ class CRG(Module):
 
         # PLL
         self.submodules.pll = pll = S7PLL()
+        self.comb += pll.reset.eq(self.rst)
         pll.register_clkin(clk100, 100e6)
         pll.create_clkout(self.cd_sys,       sys_clk_freq)
         pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
diff --git a/litex_boards/targets/tec0117.py b/litex_boards/targets/tec0117.py
index 25785767b14678cff30db03e9fd423fffa7e0576..73bb250f40ab9c416e7f5872457256ed07019fbf 100755
--- a/litex_boards/targets/tec0117.py
+++ b/litex_boards/targets/tec0117.py
@@ -26,9 +26,7 @@ kB = 1024
 mB = 1024*kB
 
 class BaseSoC(SoCCore):
-
     mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
-
     def __init__(self, bios_flash_offset, **kwargs):
         platform     = tec0117.Platform()
         sys_clk_freq = int(1e9/platform.default_clk_period)
diff --git a/litex_boards/targets/trellisboard.py b/litex_boards/targets/trellisboard.py
index d29cd0e66a6a6435f87bbf084d5b7c515c8af4a9..807e57d3810ccbae58782e5dd9c04c5ae49f9f2e 100755
--- a/litex_boards/targets/trellisboard.py
+++ b/litex_boards/targets/trellisboard.py
@@ -31,8 +31,9 @@ from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
-        self.clock_domains.cd_por     = ClockDomain(reset_less=True)
-        self.clock_domains.cd_sys     = ClockDomain()
+        self.rst = Signal()
+        self.clock_domains.cd_por = ClockDomain(reset_less=True)
+        self.clock_domains.cd_sys = ClockDomain()
 
         # # #
 
@@ -49,12 +50,13 @@ class _CRG(Module):
 
         # PLL
         self.submodules.pll = pll = ECP5PLL()
-        self.comb += pll.reset.eq(~por_done | rst)
+        self.comb += pll.reset.eq(~por_done | rst | self.rst)
         pll.register_clkin(clk12, 12e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)
 
 class _CRGSDRAM(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_init    = ClockDomain()
         self.clock_domains.cd_por     = ClockDomain(reset_less=True)
         self.clock_domains.cd_sys     = ClockDomain()
@@ -80,7 +82,7 @@ class _CRGSDRAM(Module):
         # PLL
         sys2x_clk_ecsout = Signal()
         self.submodules.pll = pll = ECP5PLL()
-        self.comb += pll.reset.eq(~por_done | rst)
+        self.comb += pll.reset.eq(~por_done | rst | self.rst)
         pll.register_clkin(clk12, 12e6)
         pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
         pll.create_clkout(self.cd_init,   25e6)
diff --git a/litex_boards/targets/ulx3s.py b/litex_boards/targets/ulx3s.py
index 316d6681a5b2147d4252231628213ebeffbd9c1f..1adc9e0c8f7570287bcdddeac1fa70e10e864ee4 100755
--- a/litex_boards/targets/ulx3s.py
+++ b/litex_boards/targets/ulx3s.py
@@ -35,6 +35,7 @@ from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq, with_usb_pll=False, sdram_rate="1:1"):
+        self.rst = Signal()
         self.clock_domains.cd_sys    = ClockDomain()
         if sdram_rate == "1:2":
             self.clock_domains.cd_sys2x    = ClockDomain()
@@ -50,7 +51,7 @@ class _CRG(Module):
 
         # PLL
         self.submodules.pll = pll = ECP5PLL()
-        self.comb += pll.reset.eq(rst)
+        self.comb += pll.reset.eq(rst | self.rst)
         pll.register_clkin(clk25, 25e6)
         pll.create_clkout(self.cd_sys,    sys_clk_freq)
         if sdram_rate == "1:2":
@@ -62,7 +63,7 @@ class _CRG(Module):
         # USB PLL
         if with_usb_pll:
             self.submodules.usb_pll = usb_pll = ECP5PLL()
-            self.comb += usb_pll.reset.eq(rst)
+            self.comb += usb_pll.reset.eq(rst | self.rst)
             usb_pll.register_clkin(clk25, 25e6)
             self.clock_domains.cd_usb_12 = ClockDomain()
             self.clock_domains.cd_usb_48 = ClockDomain()
diff --git a/litex_boards/targets/vc707.py b/litex_boards/targets/vc707.py
index 0be279889087653f0080d8ec252c5b79709423c2..4c1649faac4fe4d26a4ce14227571e46356485f5 100755
--- a/litex_boards/targets/vc707.py
+++ b/litex_boards/targets/vc707.py
@@ -25,6 +25,7 @@ from litedram.phy import s7ddrphy
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys    = ClockDomain()
         self.clock_domains.cd_sys4x  = ClockDomain(reset_less=True)
         self.clock_domains.cd_idelay = ClockDomain()
@@ -32,7 +33,7 @@ class _CRG(Module):
         # # #
 
         self.submodules.pll = pll = S7MMCM(speedgrade=-2)
-        self.comb += pll.reset.eq(platform.request("cpu_reset"))
+        self.comb += pll.reset.eq(platform.request("cpu_reset") | self.rst)
         pll.register_clkin(platform.request("clk200"), 200e6)
         pll.create_clkout(self.cd_sys,    sys_clk_freq)
         pll.create_clkout(self.cd_sys4x,  4*sys_clk_freq)
diff --git a/litex_boards/targets/vcu118.py b/litex_boards/targets/vcu118.py
index cf002722bd9bff15eb8b487a9dc2fbd372f113c6..c1deb573eb65267220ec62773f310223ca908da1 100755
--- a/litex_boards/targets/vcu118.py
+++ b/litex_boards/targets/vcu118.py
@@ -27,6 +27,7 @@ from litedram.phy import usddrphy
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys    = ClockDomain()
         self.clock_domains.cd_sys4x  = ClockDomain(reset_less=True)
         self.clock_domains.cd_pll4x  = ClockDomain(reset_less=True)
@@ -35,7 +36,7 @@ class _CRG(Module):
         # # #
 
         self.submodules.pll = pll = USMMCM(speedgrade=-2)
-        self.comb += pll.reset.eq(platform.request("cpu_reset"))
+        self.comb += pll.reset.eq(platform.request("cpu_reset") | self.rst)
         pll.register_clkin(platform.request("clk125"), 125e6)
         pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
         pll.create_clkout(self.cd_idelay, 500e6, with_reset=False)
diff --git a/litex_boards/targets/versa_ecp5.py b/litex_boards/targets/versa_ecp5.py
index 22d31526b33bd8c2c70bee8a54fe712c78f57c4a..a4d134a21c717050fedd9d14400dc0ae377148cd 100755
--- a/litex_boards/targets/versa_ecp5.py
+++ b/litex_boards/targets/versa_ecp5.py
@@ -32,6 +32,7 @@ from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_init    = ClockDomain()
         self.clock_domains.cd_por     = ClockDomain(reset_less=True)
         self.clock_domains.cd_sys     = ClockDomain()
@@ -56,7 +57,7 @@ class _CRG(Module):
 
         # PLL
         self.submodules.pll = pll = ECP5PLL()
-        self.comb += pll.reset.eq(~por_done | ~rst_n)
+        self.comb += pll.reset.eq(~por_done | ~rst_n | self.rst)
         pll.register_clkin(clk100, 100e6)
         pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
         pll.create_clkout(self.cd_init, 25e6)
diff --git a/litex_boards/targets/xcu1525.py b/litex_boards/targets/xcu1525.py
index 6c68ffc482cfbe69f163c31e099c43b8cae3f83c..dab99e537c1ed323aa5508f1d9dd29d077c71814 100755
--- a/litex_boards/targets/xcu1525.py
+++ b/litex_boards/targets/xcu1525.py
@@ -32,6 +32,7 @@ from litepcie.software import generate_litepcie_software
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq, ddram_channel):
+        self.rst = Signal()
         self.clock_domains.cd_sys    = ClockDomain()
         self.clock_domains.cd_sys4x  = ClockDomain(reset_less=True)
         self.clock_domains.cd_pll4x  = ClockDomain(reset_less=True)
@@ -40,6 +41,7 @@ class _CRG(Module):
         # # #
 
         self.submodules.pll = pll = USPMMCM(speedgrade=-2)
+        self.comb += pll.reset.eq(self.rst)
         pll.register_clkin(platform.request("clk300", ddram_channel), 300e6)
         pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
         pll.create_clkout(self.cd_idelay, 500e6, with_reset=False)
diff --git a/litex_boards/targets/zcu104.py b/litex_boards/targets/zcu104.py
index 74d554e7e27e37cc8b32fb7e462c902d4387b309..31878645a734ac37c40f1581e617ab40ee2c87c8 100755
--- a/litex_boards/targets/zcu104.py
+++ b/litex_boards/targets/zcu104.py
@@ -28,6 +28,7 @@ from litedram.phy import usddrphy
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
         self.clock_domains.cd_sys    = ClockDomain()
         self.clock_domains.cd_sys4x  = ClockDomain(reset_less=True)
         self.clock_domains.cd_pll4x  = ClockDomain(reset_less=True)
@@ -36,6 +37,7 @@ class _CRG(Module):
         # # #
 
         self.submodules.pll = pll = USMMCM(speedgrade=-2)
+        self.comb += pll.reset.eq(self.rst)
         pll.register_clkin(platform.request("clk125"), 125e6)
         pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
         pll.create_clkout(self.cd_idelay, 500e6, with_reset=False)
diff --git a/litex_boards/targets/zybo_z7.py b/litex_boards/targets/zybo_z7.py
index 6241d28dc44e0128a5d4d1e4364ac9d5d6eb441c..e8452633c05958570c34a549edfe43d1ba00c277 100755
--- a/litex_boards/targets/zybo_z7.py
+++ b/litex_boards/targets/zybo_z7.py
@@ -26,6 +26,7 @@ from litex.soc.cores.led import LedChaser
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq, use_ps7_clk=False):
+        self.rst = Signal()
         self.clock_domains.cd_sys = ClockDomain()
 
         # # #
@@ -33,9 +34,10 @@ class _CRG(Module):
         if use_ps7_clk:
             assert sys_clk_freq == 100e6
             self.comb += ClockSignal("sys").eq(ClockSignal("ps7"))
-            self.comb += ResetSignal("sys").eq(ResetSignal("ps7"))
+            self.comb += ResetSignal("sys").eq(ResetSignal("ps7") | self.rst)
         else:
             self.submodules.pll = pll = S7PLL(speedgrade=-1)
+            self.comb += pll.reset.eq(self.rst)
             pll.register_clkin(platform.request("clk125"), 125e6)
             pll.create_clkout(self.cd_sys,       sys_clk_freq)