Commit 1e1589a5 authored by Florent Kermarrec's avatar Florent Kermarrec

zybo_z7: demonstrate use of PS7 (with --cpu-type=zynq7000).

This uses a pre-generated .xci hosted on github, still need to figure out where the best location for it.
parent 8a3b453e
...@@ -36,6 +36,33 @@ _io = [ ...@@ -36,6 +36,33 @@ _io = [
), ),
] ]
_ps7_io = [
# ps7
("ps7_clk", 0, Pins(1)),
("ps7_porb", 0, Pins(1)),
("ps7_srstb", 0, Pins(1)),
("ps7_mio", 0, Pins(54)),
("ps7_ddram", 0,
Subsignal("addr", Pins(15)),
Subsignal("ba", Pins(3)),
Subsignal("cas_n", Pins(1)),
Subsignal("ck_n", Pins(1)),
Subsignal("ck_p", Pins(1)),
Subsignal("cke", Pins(1)),
Subsignal("cs_n", Pins(1)),
Subsignal("dm", Pins(4)),
Subsignal("dq", Pins(32)),
Subsignal("dqs_n", Pins(4)),
Subsignal("dqs_p", Pins(4)),
Subsignal("odt", Pins(1)),
Subsignal("ras_n", Pins(1)),
Subsignal("reset_n", Pins(1)),
Subsignal("we_n", Pins(1)),
Subsignal("vrn", Pins(1)),
Subsignal("vrp", Pins(1)),
),
]
_usb_uart_pmod_io = [ _usb_uart_pmod_io = [
# USB-UART PMOD on JB: # USB-UART PMOD on JB:
# - https://store.digilentinc.com/pmod-usbuart-usb-to-uart-interface/ # - https://store.digilentinc.com/pmod-usbuart-usb-to-uart-interface/
...@@ -64,6 +91,7 @@ class Platform(XilinxPlatform): ...@@ -64,6 +91,7 @@ class Platform(XilinxPlatform):
def __init__(self): def __init__(self):
XilinxPlatform.__init__(self, "xc7z010-clg400-1", _io, _connectors, toolchain="vivado") XilinxPlatform.__init__(self, "xc7z010-clg400-1", _io, _connectors, toolchain="vivado")
self.add_extension(_ps7_io)
self.add_extension(_usb_uart_pmod_io) self.add_extension(_usb_uart_pmod_io)
def create_programmer(self): def create_programmer(self):
......
...@@ -11,6 +11,9 @@ from migen import * ...@@ -11,6 +11,9 @@ from migen import *
from litex_boards.platforms import zybo_z7 from litex_boards.platforms import zybo_z7
from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
from litex.soc.interconnect import axi
from litex.soc.interconnect import wishbone
from litex.soc.cores.clock import * from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import * from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
...@@ -19,14 +22,19 @@ from litex.soc.cores.led import LedChaser ...@@ -19,14 +22,19 @@ from litex.soc.cores.led import LedChaser
# CRG ---------------------------------------------------------------------------------------------- # CRG ----------------------------------------------------------------------------------------------
class _CRG(Module): class _CRG(Module):
def __init__(self, platform, sys_clk_freq): def __init__(self, platform, sys_clk_freq, use_ps7_clk=False):
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
# # # # # #
self.submodules.pll = pll = S7PLL(speedgrade=-1) if use_ps7_clk:
pll.register_clkin(platform.request("clk125"), 125e6) assert sys_clk_freq == 100e6
pll.create_clkout(self.cd_sys, sys_clk_freq) self.comb += ClockSignal("sys").eq(ClockSignal("ps7"))
self.comb += ResetSignal("sys").eq(ResetSignal("ps7"))
else:
self.submodules.pll = pll = S7PLL(speedgrade=-1)
pll.register_clkin(platform.request("clk125"), 125e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
...@@ -34,13 +42,30 @@ class BaseSoC(SoCCore): ...@@ -34,13 +42,30 @@ class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(100e6), **kwargs): def __init__(self, sys_clk_freq=int(100e6), **kwargs):
platform = zybo_z7.Platform() platform = zybo_z7.Platform()
# SoCCore ----------------------------------------------------------------------------------
if kwargs["uart_name"] == "serial": kwargs["uart_name"] = "usb_uart" # Use USB-UART Pmod on JB. if kwargs["uart_name"] == "serial": kwargs["uart_name"] = "usb_uart" # Use USB-UART Pmod on JB.
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Zybo Z7", ident = "LiteX SoC on Zybo Z7",
ident_version = True, ident_version = True,
**kwargs) **kwargs)
# Zynq7000 Integration ---------------------------------------------------------------------
if kwargs.get("cpu_type", None) == "zynq7000":
# Get and set the pre-generated .xci FIXME: change location? add it to the repository?
os.system("wget https://github.com/litex-hub/litex-boards/files/4967144/zybo_z7_ps7.txt")
os.makedirs("xci", exist_ok=True)
os.system("mv zybo_z7_ps7.txt xci/zybo_z7_ps7.xci")
self.cpu.set_ps7_xci("xci/zybo_z7_ps7.xci")
# Connect AXI GP0 to the SoC with base address of 0x43c00000 (default one)
wb_gp0 = wishbone.Interface()
self.submodules += axi.AXI2Wishbone(
axi = self.cpu.add_axi_gp_master(),
wishbone = wb_gp0,
base_address = 0x43c00000)
self.add_wb_master(wb_gp0)
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq) self.submodules.crg = _CRG(platform, sys_clk_freq)
......
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