Commit 1ac1c685 authored by Florent Kermarrec's avatar Florent Kermarrec

targets/xilinx: add false path constraint between sys_clk and pll.clkin.

The SoC reset added recently creates a path between sys_clk and pll.clkin
clock domains that is reported by the tools but that can be safely ignored.
parent 016d7551
......@@ -50,6 +50,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6)
platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
......
......@@ -66,6 +66,7 @@ class CRG(Module):
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6)
platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
......
......@@ -50,6 +50,7 @@ class CRG(Module):
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6)
platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
......
......@@ -44,6 +44,7 @@ class _CRG(Module):
pll.register_clkin(platform.request("clk300", 0), 300e6)
pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
pll.create_clkout(self.cd_idelay, 500e6, with_reset=False)
platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.specials += [
Instance("BUFGCE_DIV", name="main_bufgce_div",
......
......@@ -47,6 +47,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6)
pll.create_clkout(self.cd_eth, 25e6)
platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
......
......@@ -45,6 +45,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6)
platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
......
......@@ -38,6 +38,7 @@ class _CRG(Module):
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(platform.request("clk200"), 200e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
# BaseSoC ------------------------------------------------------------------------------------------
......
......@@ -41,6 +41,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_idelay, 200e6)
platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
......
......@@ -46,6 +46,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_idelay, 200e6)
platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
......
......@@ -47,6 +47,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
pll.create_clkout(self.cd_idelay, 200e6, with_reset=False)
pll.create_clkout(self.cd_eth, 200e6)
platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.specials += [
Instance("BUFGCE_DIV", name="main_bufgce_div",
......
......@@ -39,6 +39,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_idelay, 200e6)
platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
......
......@@ -50,6 +50,7 @@ class CRG(Module):
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6)
platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
......
......@@ -38,9 +38,9 @@ class _CRG(Module):
self.submodules.pll = pll = USMMCM(speedgrade=-1)
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(platform.request("clk100"), 100e6)
pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
pll.create_clkout(self.cd_idelay, 500e6, with_reset=False)
platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.specials += [
Instance("BUFGCE_DIV", name="main_bufgce_div",
......
......@@ -45,6 +45,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6)
platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
......
......@@ -55,6 +55,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=90)
else:
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
# SDRAM clock
sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
......
......@@ -47,6 +47,7 @@ class CRG(Module):
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_idelay, 200e6)
platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
......
......@@ -55,6 +55,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_idelay, 200e6)
pll.create_clkout(self.cd_clk100, 100e6)
pll.create_clkout(self.cd_eth, 50e6)
platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
......
......@@ -49,6 +49,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_idelay, 200e6)
pll.create_clkout(self.cd_eth, 50e6)
pll.create_clkout(self.cd_vga, 25e6)
platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
......
......@@ -45,6 +45,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6)
pll.create_clkout(self.cd_clk100, 100e6)
platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
......
......@@ -39,6 +39,7 @@ class _CRG(Module):
self.comb += pll.reset.eq(~platform.request("user_btn_n") | self.rst)
pll.register_clkin(platform.request("clk125"), 125e6)
pll.create_clkout(self.cd_sys, clk_freq)
platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
# BaseSoC ------------------------------------------------------------------------------------------
......
......@@ -41,6 +41,7 @@ class _CRG(Module):
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(platform.request(platform.default_clk_name), platform.default_clk_freq)
pll.create_clkout(self.cd_sys, sys_clk_freq)
platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
# BaseSoC ------------------------------------------------------------------------------------------
......
......@@ -54,6 +54,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6)
platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
......
......@@ -51,6 +51,7 @@ class CRG(Module):
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6)
platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
......
......@@ -42,6 +42,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_idelay, 200e6)
platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
......
......@@ -41,6 +41,7 @@ class _CRG(Module):
pll.register_clkin(platform.request("clk125"), 125e6)
pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
pll.create_clkout(self.cd_idelay, 500e6, with_reset=False)
platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.specials += [
Instance("BUFGCE_DIV", name="main_bufgce_div",
......
......@@ -43,6 +43,7 @@ class _CRG(Module):
pll.register_clkin(platform.request("clk300", ddram_channel), 300e6)
pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
pll.create_clkout(self.cd_idelay, 500e6, with_reset=False)
platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.specials += [
Instance("BUFGCE_DIV", name="main_bufgce_div",
......
......@@ -42,6 +42,7 @@ class _CRG(Module):
pll.register_clkin(platform.request("clk125"), 125e6)
pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
pll.create_clkout(self.cd_idelay, 500e6, with_reset=False)
platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.specials += [
Instance("BUFGCE_DIV", name="main_bufgce_div",
......
......@@ -39,7 +39,8 @@ class _CRG(Module):
self.submodules.pll = pll = S7PLL(speedgrade=-1)
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(platform.request("clk125"), 125e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys, sys_clk_freq)
platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
# BaseSoC ------------------------------------------------------------------------------------------
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment